Commit Graph

1317 Commits

Author SHA1 Message Date
qctecmdr
be0ebcb228 Merge "disp: msm: sde: set different wd timer according to te source" 2020-07-06 21:33:00 -07:00
Veera Sundaram Sankaran
da71bb7209 disp: msm: sde: reset crtc power_event on crtc disable
Reset the power_event handle to NULL after unregistering
during crtc disable. This will avoid dangling pointer
being accessed later.

Change-Id: I73044835e8594b776eb593f2f0a4a1d2b5563531
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-07-02 16:47:02 -07:00
Orion Brody
7abc2b5b81 disp: msm: dp: cleanup in GKI module unload path
Adds null check to address segmentation faults.

Change-Id: Iafb073b88f6b52d1409b3c745bd95c69ea72ec92
Signed-off-by: Orion Brody <obrody@codeaurora.org>
2020-07-01 17:25:19 -07:00
Linux Build Service Account
b86633e592 Merge changes Iea651a2f,Idb564927 into display-kernel.lnx.5.4
* changes:
  disp: sde: add CRTC property for VM requests
  disp: msm: sde: add capability flag for trusted VM support
2020-07-01 11:36:06 -07:00
Abhijit Kulkarni
0b68037224 disp: msm: sde: fix qos perf for 90Hz panel
This change fixes the issue in selecting the correct
perf index for the 90Hz refresh rate, before this change
values corresponding to 60Hz were getting applied for this
refresh rate.

Change-Id: Id4f8af4da95f0d13d30f6316dc26dd65b61d7f79
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-07-01 10:24:05 -07:00
qctecmdr
ffa7156d3a Merge "disp: msm: sde: Add checksum support for LTM for lahaina target" 2020-07-01 07:52:03 -07:00
Yuan Zhao
5bba78331d disp: msm: debugfs interface for sde connector to do DSI read
This change implements a new feature to read the cmds response
of the panel from sde connector interface. Sde connector opens
debugfs interface for all the connectors those have support for
cmd receive operation.

Sde connector init module creates rx_cmd debugfs file at
/<debugfs-root>/dri/0/DSI-1/ for DSI-1 connector.
Format for DSI command transfer:
echo "command bytes" > /<debugfs-root/dri/0/DSI-1/rx_cmd
byte-0: the length of received buffer
byte-1: data-type
byte-2: last command. always 0x01
byte-3: channel number
byte-4: flags. MIPI_DSI_MSG_*, must be set to 0xa
byte-5: 0x00
byte-6 and byte-7: command payload length
byte-8 to byte-[8+payload length]: command payload
Example:
echo "0x01 0x06 0x01 0x00 0x0a 0x00 0x00 0x01 0x0a" > rx_cmd
The command receive operations are allowed only if controller
(ex. DSI controller) is in active state.
Read the value of panel response:
cat /<debugfs-root>/dri/0/DSI-1/rx_cmd
returns the value of this command.
nothing - failure, xx xx - success.

Change-Id: I912b65d606e248c7a886d219f4363bf7766ee7b6
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2020-07-01 00:55:51 -07:00
Yuan Zhao
263ee4756c disp: msm: sde: set different wd timer according to te source
For dual panel, if they both used sim TE, the vsync sources
were set to the same watchdog timer. That's wrong, so need to
set different watchdog timer for different panels.

Change-Id: I8a5b4c6bb86b0b640d24fbfe6517e223d313fb68
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2020-07-01 12:09:12 +08:00
qctecmdr
4fbdcba865 Merge "disp: msm: sde: wait for pending crtcs before lastclose commits" 2020-06-30 17:33:14 -07:00
qctecmdr
a0617ca0ce Merge "disp: msm: handle panel detection after a pp done timeout" 2020-06-30 15:12:07 -07:00
Tatenda Chipeperekwa
e60a0a35f8 disp: msm: dp: update voltage swing and pre-emphasis
Update the voltage swing and pre-emphasis settings based on the
latest hardware programming guide.

Change-Id: If90db2833aba2bd0613276eff22f850bf34859e5
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-06-30 14:32:59 -07:00
qctecmdr
5634bb0af9 Merge "disp: msm: sde: fix prefill line calculation for high fps" 2020-06-30 06:29:30 -07:00
qctecmdr
14d7aaccef Merge "disp: msm: sde: schedule idle notify after frame trigger" 2020-06-30 03:33:22 -07:00
Steve Cohen
5346598663 disp: msm: sde: don't advertise rotation for virtual planes
For existing HW, in-line rotation is only supported on master
planes. Remove publishing support for rotate-90 and rotate-270
on all virtual planes. Also, fixup the published support for
180 degree rotation which can be performed on all pipes that
have both X & Y axes reflections.

Change-Id: Iff248abeefeb2a100ffd833d94b429b47b6d407b
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-06-30 01:04:14 -04:00
Steve Cohen
f030fa4c2a disp: msm: sde: wait for pending crtcs before lastclose commits
If a SIG_TERM/SIG_KILL or other signal is sent to the final drm
client, the driver will be force-closed. A -ERESTARTSYS error is
occasionally seen from the interruptible wait in
msm_atomic_commit when this occurs, and causes the lastclose
cleanup to fail if any crtc is busy at that point. To prevent
this, wait for any pending crtcs to complete before calling
the lastclose cleanup commits.

Change-Id: Ib6a5e55a4b737213756cb9ed8364d5c34ab47c16
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-06-29 23:45:19 -04:00
qctecmdr
fc320f34cf Merge "disp: msm: sde: serialize rm reserve for check only commit" 2020-06-29 17:50:54 -07:00
Dhaval Patel
11b2a41dc8 disp: msm: sde: fix prefill line calculation for high fps
Fix prefill line calculation for high refresh rate
usecase and define correct number of prefill lines
for lahaina target.

Change-Id: Ib3467b9beb43de9c5faa2b1af2d8873a89c9c481
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-29 16:17:34 -07:00
Raviteja Tamatam
bbf3d7949f disp: msm: sde: modify from fixed to variable programmable fetch start
With 120 fps panels and vfp method of dfps ,the vfp is very large in lower
fps and there is huge time gap between programmable fetch start (MDP vsync)
and panel vsync.  As fence is released early timing registers are modified
by the next commit before the previous timing parameters takes effect and
this is leading to underrun. With variable programmable fetch start MDP
vsync is close to panel vsync and avoids such condition.

Change-Id: Id88b5e2957bf4af751f49f1f32327715a34b102b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-06-29 16:15:06 -07:00
Dhaval Patel
f774d21f54 disp: msm: sde: schedule idle notify after frame trigger
Existing idle notify schedule logic tries to schedule
this event before display power on. If display power on
takes more than 80ms, it triggers the idle notify before
processing first display power on frame. This patch
schedules the idle notify after frame trigger for
valid notification.

Change-Id: If94108e141b5c19d123033e9d37333e98fb987f7
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-29 16:14:56 -07:00
Satya Rama Aditya Pinapala
182d88e3b9 disp: msm: handle panel detection after a pp done timeout
The change allows for multiple TE checks during a pp done timeout.
With this change, when a timeout occurs the panel status is checked
using the default ESD check status method followed by multiple TE checks.

Change-Id: If813964bab55c5e8113721060aa5b279f30fa5e0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-06-29 15:52:01 -07:00
Narendra Muppalla
925a7687f4 disp: msm: sde: use tracing_mark_write as a node point for sde traces
This change uses tracing_mark_write as default trace 
point for msm drm driver traces.

Change-Id: I13056a8ff0513935f31bef7d8280c0a95c4394b6
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-06-29 13:03:13 -07:00
Steve Cohen
8487925f2c disp: msm: sde: remove unused output parameter in _get_tearcheck_threshold
Remove the output parameter "extra_frame_trigger_time" from this
function as callers are not using it, so it is not needed.

Change-Id: I98fcfe974c64da9ce62456a693330b898707e6b4
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-06-28 21:31:21 -07:00
Steve Cohen
36bf90e02f disp: msm: sde: adjust qsync linecount calculation
Adjust the QSYNC line count calculation to compensate for the
idle time, when no transfers are actively taking place.

Change-Id: If91eab25321eea6e6880f07605c5a9c1b7b7ee05
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-06-28 21:31:15 -07:00
qctecmdr
4d45309328 Merge "disp: msm: fix vram allocation when IOMMU is not present" 2020-06-28 04:32:57 -07:00
qctecmdr
1e80d51447 Merge "disp: msm: refactor dma buf attach device assignment" 2020-06-28 04:32:57 -07:00
qctecmdr
b299a0f04c Merge "disp: msm: sde: manage vblank refcount concurrency" 2020-06-28 04:32:57 -07:00
qctecmdr
e5e4004854 Merge "disp: msm: sde: avoid physical encoder disable(s) in trusted VM" 2020-06-28 01:57:54 -07:00
qctecmdr
1b5e5c1590 Merge "disp: msm: specify default value for msm enum property" 2020-06-27 23:15:27 -07:00
Linux Build Service Account
1a94387741 Merge "disp: msm: dp: log the status of the uevent" into display-kernel.lnx.5.4 2020-06-26 18:54:50 -07:00
Linux Build Service Account
8fb0e26527 Merge "disp: msm: sde: add xin client clock status for wb2" into display-kernel.lnx.5.4 2020-06-26 18:53:49 -07:00
Linux Build Service Account
c700dd47ea Merge "disp: msm: sde: update sspp multi rect programming" into display-kernel.lnx.5.4 2020-06-26 17:18:18 -07:00
Linux Build Service Account
7016ab641e Merge "disp: msm: dp: check ERR_PTR when creating a new connector" into display-kernel.lnx.5.4 2020-06-26 17:18:16 -07:00
Samantha Tran
d46c9286e5 disp: msm: sde: update uidle wd timer load value and fal1 threshold
Update the uidle wd timer load value to 18. This change will allow
a 15us wd timer per hardware recommendation.

Update fal1 threshold value to take the minimum of 15 or the
current setting which takes line time and target idle time into
consideration. The target idle time is also being updated from 10us to
40us.

Change-Id: Ia8d9c2070813beef18fdf342526d82cf8f82989b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-06-26 13:54:33 -07:00
Prabhanjan Kandula
690139ccd1 disp: msm: sde: serialize rm reserve for check only commit
During back to back mode set, current driver logic fails
atomic check during resource allocation with test only if
previous commit also with modeset, has tagged resources for
allocation but did not commit the resources yet. Since client
invoking atomic check before previous mode set commit complete
is an expected scenario now, instead of failing atomic check,
this change allows resource allocation for next commit also go
through by pollong till the first mode set is complete.

Change-Id: I1261b7d205bb0d886085664fab3664162a419c99
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2020-06-26 10:38:43 -07:00
Dhaval Patel
44cde01fc7 disp: msm: sde: manage vblank refcount concurrency
Vblank refcount can reach out of sync with below case
 1. event_thread triggers the vblank_enable
 2. commit_thread triggers the modeset
   2.a modeset resets the vblank refcount with mode_set
 3. event_thread triggers the vblank_disable

Event 2.a resets the vblank refcount and vblank disable
request after 2.a is going to fail. This can be fixed
by avoiding concurrency between mode_set call and vblank
request.

Change-Id: Ibb810ec90e81d63feee443f1c37dd736d5cfac0d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-25 13:54:21 -07:00
Veera Sundaram Sankaran
88037da799 disp: msm: fix vram allocation when IOMMU is not present
Allocate DSI/LUTDMA buffers from VRAM when IOMMU is not
available. Add checks in msm_gem to avoid few operations
when aspace is not available due to no IOMMU. Parse the
VRAM size from device tree, when available.

Change-Id: Iedf5749b71c2e772ac5434048520a34705c54b45
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-06-24 16:20:38 -07:00
Amine Najahi
8479ed7278 disp: msm: sde: dump clock state before entering suspend
Add debug capability to dump clocks before entering pm suspend.
This will help debug invalid register access when clocks are off
during adversarial test cases.

Change-Id: I80d19b751a3b9a1de0cc64699a21a1852d614ced
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-06-22 13:40:03 -07:00
Jeykumar Sankaran
8b032e5e46 disp: sde: add CRTC property for VM requests
Add a CRTC property to request the VM to acquire/release
HW resources.

Display driver in trusted VM boots up without HW ownership. Set
the default value of the property as RELEASED to handle resource
assignments.

Change-Id: Iea651a2fea902d95d4b954052af4ef016af15a91
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Jeykumar Sankaran
06ab29478d disp: msm: sde: avoid physical encoder disable(s) in trusted VM
VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.

In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.

In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).

Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Jeykumar Sankaran
98a6a1131c disp: msm: sde: add capability flag for trusted VM support
Add a new hw catalog flag to indicate target support for
trusted VM. Currently, the flags is set for Lahaina target.

Change-Id: Idb56492758ef580673b2ebf44fecd577a2876f1b
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Prabhanjan Kandula
f946219084 disp: msm: sde: update sspp multi rect programming
Current SDE driver allows staging of rect1 only configuration. When a
real plane is disabled sspp multi rect configuration is not updated.
This can lead to iommu faults and ping pong timeouts as framebuffer of
disabled plane is unmapped. This change fixes it by updating multi rect
config accordingly when a plane is disabled.

Change-Id: I67ae45ad0e607184c7fc49f4b220220ba1d8a2ae
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2020-06-19 16:45:29 -07:00
Dhaval Patel
31d4bb10a6 disp: msm: sde: add xin client clock status for wb2
CWB may trigger frame missed message if interrupts
are disabled on specific CPU. WB2 will only find single
interrupt status for two posted start triggered frame.
SDE driver will start checking the xin client clock
status for wb2 timeout case to trigger the valid
frame done status.

Change-Id: I16a99667116732002e6dec8a18330f8b45199387
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-19 16:28:14 -07:00
Jeykumar Sankaran
935af8104a disp: msm: sde: avoid MDSS register access during boot in trusted VM
Trusted VM will be assigned MDSS HW access dynamically only on TUI
use case start boundary. So, any HW access during the boot sequence
will result in stage2 faults. But SDE driver initializes few HW
blocks during the boot up sequence. This change fixes them by either
skipping those accesses, if those registers expected to be programmed
by the Primary VM or postponing those accesses until the HW is
assigned.

Change-Id: Ic85238c5d734e9ac993072374c1b0ae661708fca
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 15:39:03 -07:00
qctecmdr
743dc695c4 Merge "disp: msm: sde: fix cwb enable detection logic" 2020-06-19 12:44:59 -07:00
Veera Sundaram Sankaran
bd28c729e8 disp: msm: refactor dma buf attach device assignment
Assign default drm device for dma buf_attach when
IOMMMU is not present and for stage-2 only buffers.
Avoid setting lazy_unmap for stage-2 only buffers as
it doesn't have any impact without nested translations.
Assign default drm device when no device is found to
support transitions between secure usecases where
the nested context banks might not be attached back
at the prime_fd_to_handle time. These buffers would
be attached with the correct context bank device
during the delayed_import.

Change-Id: I9ccb38876d7843b4411762c7b8006ae8fca85391
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-06-19 11:36:29 -07:00
qctecmdr
1bd126d328 Merge "disp: msm: sde: add dt property for QSEED scalar HW revision" 2020-06-19 02:38:54 -07:00
Yuan Zhao
c1c2e1ca63 disp: msm: dp: check ERR_PTR when creating a new connector
sde_connector_init will return an ERR_PTR if connector
creation failed, so need to use IS_ERR_OR_NULL to check
the return value.

Change-Id: I4fee5a624261898bbd079c54705e6eaebc71bac6
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2020-06-18 19:49:05 -07:00
qctecmdr
4ebc0e1f34 Merge "disp: msm: dp: add private state to dp_mst_bridge" 2020-06-18 16:02:54 -07:00
qctecmdr
05617b0c83 Merge "disp: msm: dp: take port refcount for MST sim ports" 2020-06-18 16:02:54 -07:00
Jeykumar Sankaran
e81f110f6e disp: msm: sde: make mnoc icc paths optional
ICC frameworks may not be enabled for all the OS
environments. SDE is expected to work in the environments
where ICC paths are not defined e.g Trusted VM. Except
mnoc bus, SDE is keeping all the other paths optional.
This change adds mnoc bus to the optional list.

Change-Id: I1e3d31a3b0f49fb32041bc7e2192b014f6497267
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-18 11:28:46 -07:00