NRT path is not used for rsc enabled targets
which support inline rotation. Add changes
for rscc mode2 sequence to avoid NRT fetch
halt request and ack.
Change-Id: I60cbfa5fe1c712d1815cc689a7fd17cb99908f31
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
RSC is timing out while checking for power control register,
increasing wait times only after a poms, removes this issue.
Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Now that inline rotation is enabled and offline rotator is no
longer supported, remove offline rotator's AXI2 NRT port from
the RSCC power-collapse sequence.
Change-Id: Ib7e6637a1bcb44b4c1707208ca84c57aa875aa92
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add support for enabling and reading profiling counters via
debugfs. This change also introduces RSC rev 4 (first rev
supporting profiling counters), enabling all relevant rev 3
features as well.
Change-Id: I0326215b069a37c91072965379b0b4843916ee0a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Disable double buffer vsync configuration while
enabling clk and cmd state switch sequence. Leaving
this configuration in enable state may cause different
issues for different state switch. Clock state switch
may see a vsync delay for solver disable. Command
state switch may not update the vsync source.
Change-Id: I910fc7e33a20a04b602435020173d85a4ee926d1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Branch address offset for TCS sleep/wake has
changed for lito, add changes to support it.
Change-Id: Id938c4c85df17f6709b9533ff737cf5a0186bc09
Signed-off-by: Animesh Kishore <animeshk@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
