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35 Commitit

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43a74b1467 Merge "disp: msm: sde: simplify wait for active function" into display-kernel.lnx.5.10 2021-01-13 14:37:32 -08:00
Amine Najahi
08358fd857 disp: msm: remove use of drm_display_mode vrefresh
Use of drm_display_mode vrefresh is being deprecated in
upstream DRM framework. Downstream driver need to use
drm_mode_vrefresh API from now on.

This change removes dependency on drm_display_mode vrefresh
and replaces it with drm_mode_vrefresh API in SDE, DSI and
DP driver. In addition, it also modifies drm_display_mode clock
to align with upstream approach where an uncompressed mode clock
is required to match drm_mode_vrefresh API.

Change-Id: Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-01-13 16:08:27 -05:00
Amine Najahi
1ab772db9a disp: msm: sde: simplify wait for active function
Currently sde_encoder_phys_vid_wait_for_active function
tries to precisely wait for the first line in the active
region. This logic can be simplified by waiting a fixed
amount of time considering that this feature is only used
during hardware recovery use case.

Change-Id: Ibfd5a22c8384a184f9576275e46739a99a263323
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-01-12 21:02:05 -05:00
orion brody
d00d481360 disp: msm: move from drm_mode to msm_mode
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.

Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
2021-01-04 13:18:36 -08:00
Jayaprakash
ea5b9b3157 disp: msm: sde: always enable prog fetch and fix prefill calculations
Enabling and disabling programmable fetch dynamically
across different fps can cause dsi underflow/overflow followed
by underrun. Add changes to always enable prog fetch to handle
such cases. Fix needed_prefill_lines calculation for vfp method
of dfps since linetime is constant in this method and hence
prefill lines need to be based on max_fps. For panels whose
linetime varies with fps, the needed_prefill_lines calculation
remains unchanged.

Change-Id: Ib7b68b577ff903fc2359a8e8c4573d62d55c3828
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-11-26 14:43:43 +05:30
qctecmdr
318dfe0726 Merge "disp: msm: sde: add vblank mutex lock during irq unregister" 2020-11-23 21:20:26 -08:00
Jeykumar Sankaran
46e0ac3354 disp: msm: sde: remove HARD_RESET recovery event on frame-timeouts only
On frame timeouts, the driver should only be responsible for
reporting the error event to user space clients. Handling of
the error events should be left to the user space clients.

This change removes explicit mechanism in SDE driver to track
error events for a pre-defined threshold levels and RESET hints
sent to the user space on handling those error events during
frame timeouts.

Change-Id: I7bdf2495fae6430384b4031a7edf043b6efe88c5
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-11-19 10:33:30 -08:00
Abhijit Kulkarni
91a070feb3 disp: msm: sde: request hard reset on vsync timeout
During frame updates if vsync timeout happens, the probable reason
is pixel_clock is turned off. In such a case the recent update is
not applied on hw and can lead to issues. For example if a pipe
was detached it will not get detached since this update will not
take place.
This change detects the timeout and requests a hard reset from user mode
driver so as to ensure that all the displays are power off and footswitch
is turned off. This will ensure dpu hardware gets reset.

Change-Id: Ic9bade88b6502feb7334d239eaf669977233dbac
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-11-18 15:13:55 -08:00
Yashwanth
91291bb9c4 disp: msm: sde: add vblank mutex lock during irq unregister
Currently, during ctl reset in video mode, irq register or
unregister might result in race condition with vblank
enable/disable calls on event thread resulting in enable
cnt mismatch. This change adds mutex locks to avoid race
conditions in such cases.

Change-Id: I45aef19864475ac1b02dd8e84810eee233fc60ea
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-11-18 15:39:43 +05:30
qctecmdr
68f4129cc6 Merge "disp: msm: sde: add support for qsync min fps list" 2020-10-19 16:18:30 -07:00
Yashwanth
30b1dd339b disp: msm: sde: support qsync and vrr in same atomic commit
This change adds support to program both qsync and variable
refresh rate in the same atomic commit. During vrr
usecase, if qsync is enabled, avr ctrl gets programmed
during prepare phase as well as after configuring timing
engine. This change also handles such scenarios to prevent
double programming of avr ctrl.

Change-Id: I19461423b0ae08c8204b5edeb98e3d73ce16a21b
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-10-15 16:03:46 +05:30
Raviteja Tamatam
e5ff0b8f30 disp: msm: sde: add support for qsync min fps list
In current implementation qsync min fps is single value.
It is same for all the list of supported dfps list.
Added support for new dt entry dsi-supported-qsync-min-fps-list
corresponding to the fps supported in the dfps list
dsi-supported-dfps-list.

Change-Id: Ifd5309c2f51865a3c0d9fadb65cbcd291b6ef42b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-10-15 12:32:25 +05:30
Narendra Muppalla
9a26376b14 Revert "disp: msm: sde: add delay after porches changed"
This reverts commit 15ae91e806.

Change-Id: I11c795a8d16440a42e36e3a5bef27a6a78eec5fc
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-09-10 17:50:50 -07:00
Steve Cohen
a4be27ac7e disp: msm: sde: report intf interrupt status during underrun
Add the INTF interrupt status register value to the underrun
line count event log to assist in debugging these issues.

Change-Id: I847cb12f8b4565d5f04667e0abda5d051a6194b2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-07-29 22:14:04 -04:00
Narendra Muppalla
cea2d1cef0 disp: msm: sde: add macro for default fps
This changes adds macro for default fps.

Change-Id: Ieb1d38bd6fbfcd3fec7e2cc6e39636b6297dd0ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-07-22 13:07:45 -07:00
Abhijit Kulkarni
15ae91e806 disp: msm: sde: add delay after porches changed
This change adds 2 vsync delay after changing the timing engine
parameters namely the porches to update the refresh rate.
This ensures that panel vsync is updated as per new timing before
modifying it again.

Change-Id: I5866ea2f6f2e68bc8ce7435c4a5dbe27d8ebdd91
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-07-15 11:57:00 -07:00
Dhaval Patel
11b2a41dc8 disp: msm: sde: fix prefill line calculation for high fps
Fix prefill line calculation for high refresh rate
usecase and define correct number of prefill lines
for lahaina target.

Change-Id: Ib3467b9beb43de9c5faa2b1af2d8873a89c9c481
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-29 16:17:34 -07:00
Raviteja Tamatam
bbf3d7949f disp: msm: sde: modify from fixed to variable programmable fetch start
With 120 fps panels and vfp method of dfps ,the vfp is very large in lower
fps and there is huge time gap between programmable fetch start (MDP vsync)
and panel vsync.  As fence is released early timing registers are modified
by the next commit before the previous timing parameters takes effect and
this is leading to underrun. With variable programmable fetch start MDP
vsync is close to panel vsync and avoids such condition.

Change-Id: Id88b5e2957bf4af751f49f1f32327715a34b102b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-06-29 16:15:06 -07:00
Jeykumar Sankaran
06ab29478d disp: msm: sde: avoid physical encoder disable(s) in trusted VM
VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.

In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.

In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).

Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Rajkumar Subbiah
c0d4857a81 disp: msm: sde: adjust intf timing for widebus
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.

Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2020-04-09 14:14:55 -04:00
Jayaprakash
4536e7b2a6 disp: msm: sde: add null pointer checks
Add null check for pingpong block used during
the commit phase.

Change-Id: I3ebbcfe9c42ee6d1201a141f553bbb0a0ae97ad6
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-03-29 09:51:30 -07:00
qctecmdr
1fc486ad3e Merge "disp: msm: sde: ctl hw flush ops clean up" 2020-03-21 13:08:07 -07:00
Narendra Muppalla
68ee65353b disp: msm: sde: align timing engine vsync based on panel vsync
This change adds logic to align timing engine vsync with panel
tear check if it is supported.

Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-03-11 10:14:57 -07:00
Dhaval Patel
9438f3448b disp: msm: sde: add underrun line count information
Add underrun line count information for each underrun.

Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-02-28 11:57:47 -08:00
Nilaan Gunabalachandran
f51424f8a7 disp: msm: sde: ctl hw flush ops clean up
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-02-25 14:18:59 -05:00
Abhijit Kulkarni
7317dc417f disp: msm: sde: intf accept 64-bit compressed pixels
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.

Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-29 22:39:44 -08:00
Abhinav Kumar
e3f23771ba disp: msm: add support for variable compression ratios
Currently the compression ratio is hard-coded to either 2:1 or
3:1 in several places. This is not sufficient for new compression
algorithms as they can support higher compression ratios.

Add support for calculating the compression ratios from the source
and target bpp thereby eliminating hard-coding.

Change-Id: I6383f3d0c781193d0a9ed74df5a95d8e856edb3d
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:57 -08:00
Abhinav Kumar
27844b7b60 disp: msm: dp: remove usage of compression ratio enum from DP driver
As overall display driver is moving away from hard-coded compression
ratios, prepare the DP driver for the same by removing the usage of
the compression ratio enum.

Change-Id: I298db7d20baed8afec9f96dff8c7e950702bfec9
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:46:46 -08:00
Abhinav Kumar
c4f5050e13 disp: msm: add VDC topology related changes
Add support to configure the DPU pipeline to support VDC-m
topologies.

Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:45:35 -08:00
Jayaprakash
aad3dd4525 disp: msm: sde: update avr mode config during commit prepare
Add changes to support avr mode config update during
prepare commit which happens before gpu fence wait
for the input buffers.

Change-Id: Ib2cb5b7e1f10501914c003f6cf066b85048f79d4
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-18 12:53:56 +05:30
Jayaprakash
ad40a300a1 disp: msm: sde: allow qsync support along with VRR
Allow Qsync and VRR features to be supported independently
by display driver. Restrict the feature availability in
same composition cycle.

Change-Id: I696eb72a2b4f9451e142ffdc5acccc8987c36b6d
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-17 17:07:33 +05:30
Dhaval Patel
6f06e5cd6f disp: msm: sde: wait for specific pp_done instead of zero
2 Frames transfer pending is possible with posted start.
One ongoing frame and another triggered frame. Current SW
waits for pp_done interrupt if pending frame count is greater
than 1. It is possible that interrupt may be missed for ongoing
frame. In that case, SW should run pp_done wait for one by one
frame instead of two frames together. It allows encoder to
check the ctl scheduler status and trigger the frame done
event on time.

Change-Id: I4817842292d96747890ee70da8a5bdf9b56816ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-20 21:12:52 -07:00
Nilaan Gunabalachandran
c6092f3e66 disp: msm: sde: log intf framecount in event logs
Log hardware interface framecount during te and vblank irqs for
command and video mode panels, respectively. This will help in
debugging any missed frames.

Change-Id: Ie86f686c4cc12de6a1f31aa47d4c7a5b8a68ea55
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-06-26 11:54:51 -04:00
Samantha Tran
1ab07a4d7c disp: msm: add changes missing during snapshots
This change ports the missing changes from 4.14 to 4.19
that were missed. It includes changes up until
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").

Change-Id: Idfdfe891f146e389e3c65cc3fc4c98d93220e789
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-06-03 09:07:38 -07:00
Narendra Muppalla
3709853456 Display drivers kernel project initial snapshot
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.

Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-04-14 22:20:59 -07:00