When cwb is enabled enable software override for fal10 veto to
block fal10 entry as MDSS can keep asserting uidle if there
are no fetch clients like dim layer only usecase.
Change-Id: Ief51499d370c20fcbdda79576aee0179578650fd
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
During virt disable call, sde_enc master was used without checking
for null condition. It results in crash. This change adds required
null pointer check for sde encoder current master before dereferencing
to avoid crash.
Change-Id: I69ee17017712ea3549bfefce5975a564a5a8c2e9
Signed-off-by: Yojana <quic_yjuadi@quicinc.com>
This change adds pp_tx during DMS switch for sim panel to
prevent WD timer getting updated in middle of the frame and
creating early vsync which might result in ppdone timeout.
For non-sim panels, this tx wait is not required and is
done similar to posted start.
Change-Id: Ifec68535efa19df27e651ce0a39c03627dff2089
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
At present, idle_pc_enabled flag will be set for encoders
containing only these capabilities MSM_DISPLAY_CAP_CMD_MODE
and MSM_DISPLAY_CAP_VID_MODE. When cwb is triggered,extra
power vote will be taken during kickoff and vote remains
till cwb is disabled. In between, if primary goes into idle
power collapse, vote taken by cwb will not be removed since
idle_pc_enabled flag is not set. This change updates
idle_pc_enabled flag for all encoders based on catalog
property.
Change-Id: If4f147edbd610d0302e4d6c0a3e6b7de2c729db1
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Flush ESD status work before resetting the encoder state during
virt_disable sequence to avoid stale pointers being used in
the ESD work.
Change-Id: I4bb08a7a7ae33ad6386169667692736e554141c4
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
This change allows concurrent qsync updates along with
DMS modeset condition. With this change, qsync can be
enabled or disabled in the same atomic commit along with
MSM_MODE_FLAG_SEAMLESS_DMS condition.
Change-Id: I1b51a68f947126b25a578645e92d95c9a8ae26f5
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.
Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
allocates new resources and CTL_1 is allocated.
sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.
Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change sets CTL_UIDLE_ACTIVE register whenever uidle
is enabled and resets it only when uidle is disabled.
Change-Id: I0393d1585df4fdb79a844d04df62ac9eda949232
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Currently RSC timer register programming is optimized for updating
only during timing param changes and not during RSC state changes
with same timing. Static wakeup time computation should consider
panel jitter for RSC clk state too, else it can result in RSC hang.
This change also removes extra logic for video mode prefil lines
computation for rsc config as video mode does not enable RSC solver.
Current issue scenario exposing the hang is in dual dsi display scenario
where RSC is in clock state and static wakeup time is programmed by
not considering panel jitter, after suspend/pmsuspend while waking up
if RSC switches to command state if primary enabled first and vsync
may arrive much early based on the panel jitter. RSC hw can not handle
if TE arrives earlier than static wakeup time causing RSC hang.
Change-Id: I1434fdd71eb04fdbe22b3601500493c818e9126d
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.
Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.
Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
When disabling an encoder with multiple physical encoders, the
intf mux must be cleared on all interfaces. Currently only the master
physical encoder is being cleared, leading to possible DSI
underflow errors. This change ensures that the mux is cleared
on all interface blocks.
Change-Id: Idb1b96fd65545e3599100e70ace22bc3837d7233
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.
Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Add a utility function to check if HW has been handed over to
another VM.
Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Early wakeup ioctls from perf HAL driver can access display HW
registers and come as a sideband to atomic commits. Since the
atomic validate checks are not part of this code path it's
possible for HW access to occur during a trusted UI session.
Prevent this whenever the HW is not under this VM's ownership.
Also, move the VM ownership check for the register/deregister
event ioctl to cover both the CRTC and connector events since
new connector events are being added which can access HW.
Change-Id: I39660ae60e7e8f8a405e819c43ec42fbac3f492a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.
Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.
So remove clearing cur_master in encoder enable function to avoid the
race condition between modeset and irq callback.
Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.
Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.
Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.
Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.
Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Check if sde_enc->crtc exists before using the variable
to avoid possible NULL dereferences.
Change-Id: If7b56c3b3ad3525b3efc22b6536a2dc5c865da48
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Topology in sde_encoder is no longer used, so remove this
variable from sde_encoder.
Change-Id: Iba02ae690d81d39252d0df83882a72e35f2916ec
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Canceling delayed_off_work in encoder pre_modeset might not be
executed in all cases, but the following encoder enable might
initialize the work.
This will lead to list corruption as delayed_off work list node
is reinitialized before removing from linked list.
Move canceling delayed_off_work to start of encoder mode_set to
ensure work is canceled before reinitialization.
Change-Id: I38687604f2eedced308ea02019c162022725534e
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
In the event of panel dead scenario, it is possible to receive a
mode set call before the panel has recovered. When this happens,
display should select watchdog TE as the vsync source.
Similarly when detecting a write pointer timeout, if the panel is
dead then watchdog TE should be or has already been configured and
display should not make a change to this vsync selection.
Change-Id: I732c75e54d734b00889151b914b0749ae1f27d08
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In video mode for fps greater than 60, perf cpu dma latency votes
are not removed during idle fallback. Made changes to remove and
add the perf cpu dma latency votes during idle fallback and idle
exit scenarios respectively.
Change-Id: I8dffc743bd48c96a6022935f71057a0223d9696e
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
While setting up vsync source, display info is used to decide whether
or not watchdog TE should be used. This change passes display info
as a parameter to vsync setup rather than using the encoder's display
info which is not updated in the case of panel dead error.
Change-Id: I928ee2012eec7bf63f4ba3538082bc3e47d5e99d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change adds logic to determine dsc switch based on
the connector property "CONNECTOR_PROP_DSC_MODE" and
performs seamless DSC switch if there is any change in
DSC configuration. The connector property is populated
in msm_sub_mode based on which suitable mode is selected.
Change-Id: Ifc4931f16dfb814781bc1d72b103e09103e6bfee
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
During modeset, private mode changed is detected from
msm_display_mode which is present in sde_connector_state.
In the current code, sde_connector_state is found from the
drm_connector variable which will not be valid
during atomic check phase and new connector state is
required here. To handle this, drm_connector_state is passed
along with the drm_crtc_state while detecting
msm_atomic_needs_modeset condition.
Change-Id: I62c162eff6e1c091cb05b3f049a40a0f25b710ba
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
During high framerate cases, disable RSC solver mode as there
will not be much power saving to be done. Disabling is decided
through panel timing node property.
Change-Id: I178170a5ab1b7e31b92ae3019e0147c05a282850
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.
Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
