This change adds DSI pll support for 10nm architecture.
Change-Id: I3819dd828dbcc168b115bd718c5d656ea9fd12c8
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Trusted VM will be granted access to MDSS HW dynamically on
usecase boundary. As a result, all the attempts to access
HW before the assignment, including the probe time access
will result in Stage 2 faults. This change skips the
PLL clock registration during probe as the clocks will not
be controlled by the VM.
Change-Id: I326f4a775796cd95dcf398449b08f2682e4aca43
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Add function to parse pll_codes from dfps_data_region, and the
pll_codes are used as trim_codes for RFI.
Change-Id: Ic81529cd685f17012809fb68cefc4b36cb1172ca
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add function to parse pll_codes from dfps_data_region, and the
pll_codes are used as trim_codes for RFI.
Change-Id: I5b16be94a9e47dff515dea036839f74c2ddd8824
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
DSI PLL is tightly coupled with DSI PHY. This change removes
separate DSI pll driver and makes DSI pll as a subnode to DSI
PHY which is an accurate way of representation. In addition, this
change adds support for 5nm DSI ctrl and PHY revisions and adds
DSI pll support for 5nm. Remove support for older DSI pll revisions
such as 7nm, 10nm, 14nm, 20nm, 28nm.
Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
