Commit graph

13 Commits

Autor SHA1 Nachricht Datum
Prabhanjan Kandula
d863e18638 disp: msm: sde: fix dsc initial line caluclation
Current DSC intial line calculation is giving extra line on top of
recommended value from systems since number of active soft slices
considered is wrong. Fix the number or usage of active soft slices
in an encoder to align dsc initial line with recommended setting.

Change-Id: I321260e22b7824b8c481a55b54831ce9535661cc
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:48:52 -07:00
Prabhanjan Kandula
d5390da6c7 disp: msm: Update dsc 422 and 420 encoding settings
Update dsc configuration and pps programming for 422 and
420 encoding as per the DSC hardware spec.

Change-Id: I4251614cdcd550ed724b1d0dba4846cada4b5392
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:47:34 -07:00
Andhavarapu Karthik
59c3e9ef10 disp: msm: sde: program ob_max_addr based on dsc native422 support
Current code does output buffer max_addr calculation based on dsc id.
Made changes to calculate ob_max_addr based on dsc native422 support.

Change-Id: I01922750f1e9d6cb45615acc1c473891fc648e5d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-05-19 16:35:41 -04:00
Tatenda Chipeperekwa
c6257272d4 disp: msm: fix compilation errors for dlkm compilation
Fix dlkm compilation errors that are due to the use of -Werror
flags used by the build system.

Change-Id: I5e1e9bc63c1361d73e4930aab123212717872ecb
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2021-03-22 15:25:36 -07:00
Linux Build Service Account
2bdc128bfc Merge "disp: msm: sde: fix dsc hrd delays register bitmask" into display-kernel.lnx.5.4 2020-08-19 01:54:39 -07:00
Amine Najahi
788a4482d0 disp: msm: sde: fix dsc hrd delays register bitmask
Fix bitmask used when programming dsc hrd delays register
to allow 16 bits value.

Change-Id: I0044dcd4bdc4608b40a544b1856dfaa19e1717a3
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-08-13 10:19:17 -04:00
Abhijit Kulkarni
7456f4b946 disp: msm: sde: reset ICH on partial update
This change programs both the ich_rst_manual_override and the
ich_rst_manual_value in the DSC encoder to override the hw behavior.
This override is needed to ensure the position of ich_reset is not
changed during the PPS session.

Change-Id: Ia7619a97beeea495706b4327c34fc49ef2298583
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-08-06 10:11:01 -07:00
Abhijit Kulkarni
4e37cc3f17 disp: msm: sde: right only pu support
This change add right only pu support by allowing the dsc to be
flushed when one of the dsc is getting disabled. Since the crtc
swaps the mixers in case of right only partial update, this change
fixes the active display mask passed to encoder so that always the
left only dsc gets programmed. This change also fixes layer mixer
configuration where only one layer mixer is driving the partial
update, the other mixer's configuration is disabled.

Change-Id: I2dd2e9a347797bfe07c90e0ca7f999d151fba933
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-07-23 14:40:03 -07:00
Amine Najahi
b121756b5d disp: msm: sde: adjust DSC encoders to support all 4LM topologies
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.

Change-Id: I5358d60634070bdb26059056db884ad4161c073e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-28 19:25:09 -07:00
Alisha Thapaliya
e2f98dc79b Revert "disp: msm: sde: adjust DSC encoders to support all 4LM topologies"
This  reverts commit 6a50aedbfa.

Change-Id: I3570b18728cfad2843ca7f3a7d0276cda32c9492
2020-05-14 11:51:15 -07:00
Amine Najahi
6a50aedbfa disp: msm: sde: adjust DSC encoders to support all 4LM topologies
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.

Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-06 14:16:40 -04:00
Abhijit Kulkarni
970ea08286 disp: msm: sde: fix issues with dsc config
This change fixes issues which causes corruption for dual dsi
dsc panel. It fixes the number of slices configured on
dsc hw block and handles deriving correct picture width from
mode timings. Additionally it fixes the core max buffer sizes
used by the hw block.

Change-Id: Iec0ef80528425ffcb5f29d469bd181eb7040de16
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-02-12 22:19:15 -08:00
Abhijit Kulkarni
a00714beae disp: msm: sde: add DSC 1.2 implementation
This change adds implementation to configure DSC 1.2 block
registers to enable both dsc1.1 and dsc1.2 specifications.

Change-Id: I2307d7dace05bf20384d3221e9aca65e296b12bd
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00