PCIe window select config reg update goes on different NoC and
actual PCIe device register access goes on the different NoC.
If there is delay in window select reg config, it can result in
access some other PCIe IO memory access and will result in actual
register write lost issue. Make sure to flush the window select
reg write before actual device reg access.
Change-Id: I1fe17aad7ae8fd5dea7a618273d9cd813b236a85
CRs-Fixed: 2687676
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
Do batched invalidate of tx completion descriptor to avoid
unnecessary D-cache miss for 32 byte size descriptor.
Change-Id: Ia580fe78dcef5b36f117aaad171a2df6d0e34966
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
In current monitor status ring implementation,
on pdev_attach, (srng->num_entires – 1) entries
(to keep one entry slot between hp and tp)
are replenished and last entry is not replenished to HW.
With qcn9000 monitor mode HW enhancements, status and destination ring
can be made lock-stepped.
for qcn9000 lock step is achieved by making monitor status ring
follow the monitor destination reap for a PPDU
However in existing flow during attach monitor status replenish logic
do not fill last entry but is filled up during first subsequent reap.
for first ppdu, i.e. after reaping destination ring,
when status ring is reaped, as first entry (hp = srng->num_entires – 1)
in status ring is NULL, so lock-stepping is not achieved.
To address this issue for qcn9000 as well as HK:
a. Replenish last entry in monitor status ring during attach
b. Modify src srng peek API to peek it from hp+1 entry
c. Introduce new HAL API get cur desc and move next
d. Remove WAR to skip status ring entries if DMA is not done
Change-Id: I60b8e7c075253d37e6b849a9b24f473c5afce82c
CRs-Fixed: 2626049
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Fix macro name to enable delayed register writes.
Donot use delayed register writes for non fastpath access.
Change-Id: I235116ab3df5cb26bbfbb72de4ac6ed4b363a13a
CRs-Fixed: 2645865
As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.
Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).
Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
Add HAL layer changes for full monitor mode.
Define HAL API and Data structures to read sw_monitor_ring
descriptor.
CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
In current monitor status ring implementation,
on pdev_attach, (srng->num_entires – 1) entries
(to keep one entry slot between hp and tp)
are replenished and last entry is not replenished to HW.
With qcn9000 monitor mode HW enhancements, status and destination ring
can be made lock-stepped.
for qcn9000 lock step is achieved by making monitor status ring
follow the monitor destination reap for a PPDU
However in existing flow during attach monitor status replenish logic
do not fill last entry but is filled up during first subsequent reap.
for first ppdu, i.e. after reaping destination ring,
when status ring is reaped, as first entry (hp = srng->num_entires – 1)
in status ring is NULL, so lock-stepping is not achieved.
To address this issue for qcn9000 as well as HK:
a. Replenish last entry in monitor status ring during attach
b. Modify src srng peek API to peek it from hp+1 entry
c. Introduce new HAL API get cur desc and move next
CRs-Fixed: 2626049
Change-Id: I7da6cd6006243cbca2151da22a31a6f5ed0015f3
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Sometimes the register write in windowed region
are not going through, thereby retaining the
previous value, which can be incorrect for a
certain mode of operation for the driver.
This kind of incorrect register values, due to
a register write not succeeding, can lead to
unwanted issues. Also the simple logging of
any such occcurence can be over-written in the
logs, thereby going unnoticed.
Add a HAL level statistics to maintain the
count of such failed register writes.
Change-Id: Ib5e98705c23f0c916cb85f518576663710eb30e0
CRs-Fixed: 2611839
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
Command ring is now renamed to credit ring on QCN9000
and used for credit based flow.
Renaming the ring to give meaningful name.
Change-Id: I726aed19477fcfb256e4e0cca8ddb9389035b58c
CRs-Fixed: 2562640
Define shadow register value as 0 in else case where none
of the chips supporting SHADOW configuration are enabled. This
is needed for low memory configuration profiles where
QCN9000 and QCA6290 are undefined.
Change-Id: I6281568e830b506707aeb96d3ea03811cc1de8a7
Force wake request is sent before register write. If this req
fails check if FW is down or host is in recovery before
asserting.
Change-Id: I6d31b1f95b68ae4e462f59ed32ed933de55cacae
CRs-Fixed: 2601364
Link descriptor were getting freed by the pointer
of the previous freed link descriptor. This patch
fixes by copying the address of the current in a
local descriptor info and using it to free the
current.
Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6
CRs-Fixed: 2577624
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
Increase the force wake timeout to 100ms for
debug builds as mhi requires 100ms to
wake up.
Change-Id: Ida0b1287a86a5a97fd2d9c80fee4e677eea86cbe
CRs-Fixed: 2552815
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
Added change to modify ce flags for Pine.
Also made changes in window enable bit
Change-Id: Id080be53d14450cb6d9376fc810177bce26a2869
CRs-fixed: 2507441
The reo destination ctrl registers
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR and
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR are used for mapping
msdu packets to different reo rings.
For QCA6390,
reo remap values varied from 0 - 7 so every 3 bits in
the register were used to map to a particular reo ring.
For QCA6490,
reo remap values vary from 0 - 9 as two extra reo rings are
added so we are using 4 bits in the register to map to a
particular reo ring.
Use the macros directly provided in the header files
to map reo rings.
Change-Id: I6d64266d3b388b3453b7df959048e3d693cf0a40
CRs-Fixed: 2544102
If CNSS platform driver and wlan host driver try to write
window register at the same time, conflict happened which then
register write failed.
Use the window register lock shared from CNSS driver to avoid
the conflict.
Change-Id: Iccc4e60e4f5eed995ec6aa53b024f3f96a2619a0
CRs-Fixed: 2534408
Check if REO ring is near full at the end of dp_rx_process. In case the
ring is near full, reap the packets in the ring (and replenish, send to
upper layer) until the quota allows. Ignore the HIF yield time
limit in such cases.
This change is needed to prevent back pressure from the REO ring(in case
it gets full). Backpressure from REO ring (to LMAC) may lead to a
watchdog and eventually a FW crash. Hence, avoid such a scenario by
reaping as many packets as the 'quota' allows when the REO ring is in
aforementioned condition.
A sid-effect of this change would be that at times the RX softirq may run
longer (till the quota limit) than the configured HIF yield time.
However, this logic is not expected to kick-in in perf builds. The issue
is reported for a defconfig build where lots debug options are enabled
in the kernel which can slow the processing down.
Change-Id: I2eb6544c159ec5957d10386b1750fd96473fe13a
CRs-Fixed: 2540964
During hal write register first device force wakeup
request is done. If force wakeup request fails register
write is not done and the execution continues. This leads
to NOC erros in REO ramap register cases. As in later point
of time packets will be coming on wrong reo2sw ring and at
the destination side channels are not enabled. When NOC error
happens the current system is of no help to root cause as the
write fail happened way before. So do panic if pci wake request
fails which help to root cause the reason for failure.
Change-Id: I30d3f0a7858f3d4af96a80f69ba59764c9a7c8e9
CRs-Fixed: 2541061
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Add the following macros:
1. HAL_REO_CONFIG
2. HAL_RX_MSDU_DESC_INFO_GET
3. HAL_RX_LINK_DESC_MSDU0_PTR
Add the relevant function pointers to
retrieve the descriptor info from the
above mentioned macros based on a
given chipset.
Change-Id: If44ae3d91397f1b1b0c36a49ce56a2c5e719434e
CRs-Fixed: 2522133
Currently after runtime resume all SW2TCL data and reo cmd
srng rings hp and tp value are flushed. In case of IPA
offload case SW2TCL3 righ hp value will be updated by IPA
and not by host. In case of runtime pm enable host is
setting the value to zero as part of runtime resume which
results in incorrect hp value of SW2TCL3. As part of this
change set flush event for rings which are accessed by host
during link down state and after runtime resume flush the
rings for which flush event is set.
Change-Id: I5c9afa708277cf3a6e6d5ef99447bc21f88cfdcf
CRs-Fixed: 2514621
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Add code to remove void pointer usage for hal_srng
and use opaque pointer dp_hal_ring_t instead.
Change-Id: I6907f7376d7fe3c9180b8795bd96f49fead2ec64
CRs-Fixed: 2484404
Make change to remove usage of void pointers for
ring descriptors and instead use a opaque pointer
dp_ring_desc_t.
Change-Id: Ia1e9a3da9eaa3cccf297b2135b52a72f2fe21431
CRs-Fixed: 2484409
Add code to remove void pointer usage for hal_soc
and introduce opaque pointer to be used intead of void
from dp layer into hal layer
Change-Id: Ia38571174c6ed79558d0f0c9cd1a0f4afaa66483
CRs-Fixed: 2480857
Reducing the log level of debug log to avoid console logging
and instead get it on the cnss diag log.
Change-Id: Ie5a1eb6f45ffa97790d91528a173b16319ec760b
CRs-Fixed: 2486057
In register select window if the register offset falls
in the last stored register window in driver, register
window remap is not done. There is a case if platform
driver accesses the hardware registers and remaps the
register window, then driver wont be aware of this and
have the wrong cached register window. So when driver
tries to write or read it selects the wrong register
window and accesses wrong register address. So fix this
by always doing the register window remap.
Change-Id: Ic38cc8cc3d9d82a3534f5ea356027db324c9fe13
CRs-Fixed: 2477771
1. Record hp/tp for ce dst and status ring to keep
a track of the last reaped and posted buffers.
2. Add union ce_srng_desc to record ce srng descriptor
information.
Change-Id: I6f4728893d629c60f676826bf806b725326fb83d
CRs-Fixed: 2465492
The current calculation of head/tail pointer for
srng gives an index in the array by skipping
entry_size dwords.
The head/tail pointers are preffered to be the
index values like in the srng registers, which
brings them in alignment with the other usage of
head/tail pointers.
Fix the calculation of head/tail pointers for srng
by avoiding the division by srng entry size.
CRs-Fixed: 2469332
Change-Id: If9a167f3fac3cb39ebe59618e9ad2224d9e54bcc
Add support to configure any HAL SRNG descriptor to
be allocated from cached memory area. This is to
optimize of CPU cycles spent on uncached
memory accesses. Also added prefetch of cached
descriptors
Change-Id: I2544e8596d48e2f5549bf687a764c16d73397545
CRs-fixed: 2267945
If there's a HW duplicate rx descriptor from hardware,
it'll cause a NULL pointer issue in
__dma_inv_range in dp_rxdma_err_process.
In this case, skip procssing it as a workaround.
CRs-Fixed: 2398327
Change-Id: I5639e5fc9a3a06e6762448ec7cb2ea58d9ae8160
The following changes are made
-Yield dp_rx_process if poll time exceeds
-Yield dp_tx_comp_handler if poll time exceeds
-Interrupt statistics to track various interrupt contexts and
corresponding interrupt masks
-Add poll times histogram buckets to NAPI stats
Change-Id: I8c7a6bbbb97c7b3dd1dde6ac3a97113c433086a2
CRs-Fixed: 2423879
