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67 次代码提交

作者 SHA1 备注 提交日期
Gopikrishnaiah Anandan
33404efc1c drm: msm: fix active pipe index
Active pipe index will be incremented when free entry is found with the
current implementation. All the indexes will not be used and there is need
to have special handling for last index with current implementation.
Change adds a break in the loop and simplifies the handling.

Change-Id: Ic74ad2aef791ba9c81acb19e85f44edf4d59e434
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-04-01 18:18:31 -07:00
Gopikrishnaiah Anandan
078d42797b disp: msm: add support for no blend planes
Some of the features in the DPU hardware needs planes to be staged but
it should not be blended in the layer mixer. Change adds support for drm
driver client to set the blend type on the plane and updates driver code
to skip staging the plane.

Change-Id: I1e8c7f6ce5617820ea8b24419e0d4d27b481819b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-03-31 14:07:49 -07:00
Samantha Tran
83ff89732a disp: msm: sde: remove check comparing encoder's crtc and crtc
This change removes the check comparing encoder's crtc to the
crtc passed in. This check was required up until commit 70486d209c
("disp: msm: sde: remove vblank cache logic"). Now that iteration
is only happening over encoders in the encoder mask, there is no
need to check for a matching crtc to ensure it is valid.

Change-Id: I4ee08061e6c8679fe03f42cf2f889704c99526e5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-03-29 16:54:10 -07:00
Lakshmi Narayana Kalavala
1f331b536f drm: msm: sde: handle event disable failure
If unregister event fails to succeed due to invalid params
or due to inappropriate hardware configuration, The callback function
is not deleted from the irq table. This leads to list corruption
issues in the subsequent calls to event enable and disable.

Change-Id: I549bd15b07b9a3b04c0f0a239bd85748acf7d473
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2020-03-29 16:53:35 -07:00
Nilaan Gunabalachandran
7ebf621320 disp: msm: sde: check new connector state for secure context
During wb use case, if any of the input buffers are secure,
the output buffer must also be in secure. In order to
successfully check if output buffer is secure context,
kernel needs to access new connector state.

Change-Id: Ia0124418eac35cf6d3301603e39ed45b971e2665
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 16:52:36 -07:00
Nilaan Gunabalachandran
868fb9cb24 disp: msm: sde: fix frame event signal for cwb
Submit a cwb frame event signal to notify the crtc that cwb
is completed. Currently cwb also uses the same frame done
event as primary. When a single cwb commit is completed, because
cwb is on a slower path there is a race condition in which the
subsequent frame done event for primary clears the refcount.
This fix isolates the events and removes this situation.

Change-Id: Ic3e18302eb8a497cbd7a00f271de2ab320576c83
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 16:52:27 -07:00
Lakshmi Narayana Kalavala
c3010cfe77 disp: msm: sde: initialize list head of irq node
List head should be initialized after the irq node is allocated.
Change initializes the list head of the node.

Change-Id: I495751fcf2422bba3f39a0719e2d76738b691dd9
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2020-03-29 16:52:00 -07:00
Yashwanth
d8cabe36c1 disp: msm: sde: add uidle property to the crtc
This change adds support to check whether uidle
is supported for given target.

Change-Id: Icd7ef36eeefcd8d1fc3c960dc7c7560469945408
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-03-29 16:51:27 -07:00
Krishna Manikandan
1b0fa415a0 disp: msm: modify stage for dim layer during atomic set
Stage property is modified for dimlayer during atomic
set property phase. This avoids any commit failure occurred due
to dimlayer checks during atomic check phase.

Change-Id: I4ff3d83a5aa9d6446fd4955f6c29854acf93bc68
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:51:15 -07:00
Krishna Manikandan
83f31f5ebb disp: msm: add support to expose base layer staging property
Add support to expose base layer staging property to HAL.
In those targets where base layer staging is enabled in mixer,
layer with zorder 0 will be staged as base layer.

Change-Id: Id825357c61ac6913bdcb8a184fc501236519d5dd
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:51:05 -07:00
Krishna Manikandan
e99063c7a3 disp: msm: stage layer with zorder 0 as base layer
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.

Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-03-29 16:50:44 -07:00
Nilaan Gunabalachandran
2e0702c7e6 disp: msm: sde: check input & output buffer for secure context
During validate, kernel should check if input buffer frame
buffer for wb conn is in secure context. If so, the output
buffer must also be secure context, or fail validate before commit.

Change-Id: I38e50f8b2ac71c8532d9d44df08850bf33180c41
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-03-29 09:54:43 -07:00
Veera Sundaram Sankaran
bceea4e1fe disp: msm: sde: reset ctl on autorefresh disable failure
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.

Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-28 23:07:32 -07:00
Raviteja Tamatam
69c24f5a32 disp: msm: sde: update BW_INDICATION programing sequence
BW_INDICATION indication must be programed before BWI_THRESHOLD.
Otherwise, it will revert to legacy behaviour and rsc wakeup is
delayed by one vsync causing janks. In current code BW_INDICATION
is done after LM/SSPP programming and plane fence wait. Moved the
perf_crtc_update before this and just after ctl prepare configuration
to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time.

Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-03-28 23:06:51 -07:00
Samantha Tran
5880783aa3 disp: msm: sde: avoid resetting blend stage in every commit
Move blendstage initialization to the atomic begin path in the
case where mixers are not setup. Additionally, clear all
blendstages during crtc disable to clean up registers.
This will avoid resetting each of the blend stages in every
commit and then writing only to the layer being used.

Change-Id: Idf7cb3e17de37034c2060f2563bc082fceb5cae9
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-03-06 12:29:06 -08:00
Gopikrishnaiah Anandan
1690129d60 drm: msm: handle resolution switch for LTM
DPU configuration should be changed when resolution switch happens at
the layer mixer level for ltm feature. Driver should mark ltm properties
as dirty when resolution switch happens. Change handles dynamic resolution
switch for ltm by marking the properties as dirty.

Change-Id: I5ffc8e74c42da6c2902eb42fd2e3ed1b9f9e3e4c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-02-17 07:52:01 -08:00
Amine Najahi
af07b8a5d4 disp: msm: sde: add support for hardware based rounded corner
Add support for hardware based rounded corner part of
color processing framework.

Change-Id: I3e5f4dac6ffc759bb940215b7621ac716f255169
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-02-16 01:03:58 -08:00
Steve Cohen
6a2bd3aabb disp: msm: sde: reduce complexity for sde_crtc_install_properties
Reduce the cyclomatic complexity for installing CRTC properties.

Change-Id: I42572413713b3a079fb5edcaa25d9050b76adc6c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-02-04 16:04:35 -05:00
Amine Najahi
119b84ea5c disp: msm: sde: add atomic check handling in cp framework
Add atomic check handling in color processing framework.
This will check cp features during the validate phase.

Change-Id: I6d94316a749ad247aec0554c31fa56af6db61ab6
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-01-30 14:38:57 -05:00
Abhijit Kulkarni
dc8e0291e4 disp: msm: sde: move dsc implementation to a new file
This change moves the DSC implementation into a separate file.
This is required to add support for new compression algorithms.
This cleanup change also, moves struct sde_encoder_virt
declaration to the encoder header file.

Change-Id: Idc3b96e65fcce2a7ee6e17af604cec0cb574f6f7
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:30:43 -08:00
Narendra Muppalla
a0b168f7b3 Config: enable techpack display driver compilation for lahaina
This change enables display drivers code compilation
for lahaina target and current location of header files
is replacing the header files in usr/include/drm directory
before installing display specific header files. This change
ensures both the drm and msm_drv header files are exported
to user mode clients.

Change-Id: If6fc347598b902e670b7206dbcb82fe0740b3984
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-01-14 14:10:45 -08:00
Narendra Muppalla
b02d482e6a disp: msm: sde: remove sde wrapper for clock set flags
Since clock set flags api is deprecated for new target, this
change removes sde wrapper and removes LUT memeory retention logic
from crtc module.

Change-Id: If37ec780913668c1a43f8a71e79249679526bd34
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-11-26 16:25:28 -08:00
Narendra Muppalla
d1d9ae8b19 Disp: Snapshot change for lahaina display driver
This snapshot change adds downstream support
for drm 5.x+(msm_lahaina branch) linux kernel.

Change-Id: Ia691c95da155a00e449c91a2f1a5b20a8e71aed4
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-11-24 12:30:51 -08:00
Ravikanth Tuniki
1e60728ab8 disp: msm: sde: Fix 32-bit compilation issues
1.Typecast to avoid distinct pointer type comparison
2.Keep DMA mask aligned with api definition.
3.Add Suffix for literals
4.Remove multfrac func to avoid uncompatible division.
5.64-bit division( operator "/") on 32-bit platforms is not supported.
  Using platform independent API's here

Change-Id: I0e7305418e53876bd1adf00c1963f85cbdf980cc
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
2019-10-24 14:48:40 +05:30
Veera Sundaram Sankaran
e4a7d473f9 disp: msm: sde: handle all error cases during sui transitions
During secure-ui, the SMMU, MISR and VBIF states
are altered based on the enable/disable of secure-ui
which is followed by the scm_call. Failure in any of
the steps would lead the system to an unstable state.
Address all the failures and revert back all steps
to get the system back in original state to avoid
any issues.

Change-Id: I736c6cf018c5992ec33806c00e58bf56b818b8a7
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-10-21 11:41:14 -07:00
Krishna Manikandan
a4c2827a47 disp: msm: sde: add support to handle mdp limits property
Add support to handle mdp limits property which
can be used to represent maximum possible limit
for different usecases like sspp linewidth,
bandwidth limit etc. Each child node can be
used to describe each property.

Change-Id: I4b0645201fa29bba1a083e2df4733bec07f0dd96
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2019-10-09 11:06:52 +05:30
Gopikrishnaiah Anandan
097da1a65c drm: msm: add support for ltm off event
Clients of local tone mapping engine need to know when hardware block
was turned off, to enable mutually exclusively display features.
Change adds support for ltm off event notification via custom event
interface of drm.

Change-Id: Ibfe2f85eadb0b939deee56194387b51b1e5ca8b9
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2019-10-01 14:03:49 -07:00
Veera Sundaram Sankaran
b7ba56ff00 disp: msm: sde: fix inline rotator downscale ratio check
During the validation of inline-rotator downscale ratio,
in the plane atomic_check phase, the client_type is
derived from the crtc->state. This leads to wrong
client_type as in check phase, it has to be derived
from the new crtc state. Fix it to derive from
new crtc, which would in turn be used to get the
correct inline-rotator downscale ratio.

Change-Id: I109fc6fd81182b1cda1c4feefbf421d3fab433c7
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-09-18 13:28:17 -07:00
Veera Sundaram Sankaran
4776221d5b disp: msm: sde: fix panel mode check during SUI validations
During SUI validations and transitions, the encoders
are iterated to find the panel-mode. If concurrent
writeback is enabled, it is assumed as video mode.
Add check to consider only the built-in display
panel mode during sui to avoid wrong interpretation.

Change-Id: I2901eb29a0799571a95f6ab6f9f3f2c6154424c5
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-09-12 13:56:30 -07:00
qctecmdr
66a975dcce Merge "disp: msm: sde: fix panel mode check during secure transition" 2019-09-10 18:42:23 -07:00
qctecmdr
0ce6ca8992 Merge "disp: msm: sde: revert to previous smmu state upon failure to switch" 2019-09-08 11:20:10 -07:00
Veera Sundaram Sankaran
c24da68432 disp: msm: sde: fix panel mode check during secure transition
During transition from sui to non-secure if concurrent
writeback is enabled, it is incorrectly assumed as
video-mode panel. This leads to wrong video-mode
validations and false errors. Fix the check to get the
panel mode only from the primary display.

Change-Id: I3da3076d17cfe2314118b947133cbfc55581a195
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-09-06 16:28:56 -07:00
Lei Chen
3d1b73abc6 disp: msm: sde: Get connector roi state even PU disabled
Partial update will be disabled while panel operating
mode switch from command to video.
Display validation will be failed once CRTC and connector
ROI state are not the same.
So add this change to get connector roi state even partial
update is disabled.

Change-Id: Iebb1d001c1c11b659141ce301400704c16390ee6
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2019-09-05 19:43:43 -07:00
Samantha Tran
ad97f0cf4d disp: msm: sde: revert to previous smmu state upon failure to switch
This change saves the previous state before moving into the transitional
smmu state, during secure-display/secure-camera usecases. Upon failure
to complete the transition, set smmu state to the previous state.
Previously, smmu state was staying in transitional state.

Change-Id: I1a78ddcf6ac1c7ea66c8c2095cd1a6d6160647a1
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-09-04 15:16:27 -07:00
Nilaan Gunabalachandran
233ded8506 disp: msm: sde: consider num DS for mixer width
Helper function is returning the width of single mixer. During
atomic crtc check, the number of destination scaler is not
considered before width check and can fail possible higher
resolutions. The mixerwidth should be taken as a multiple of
num_ds_enabled.

Change-Id: Id9e5e0ccf0cebb54d2a242e039d8dc3676b3729f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-23 12:20:41 -04:00
qctecmdr
73175fb95a Merge "disp: msm: sde: Correct initialization value for frame count" 2019-07-19 05:17:05 -07:00
qctecmdr
3ab9638e45 Merge "disp: msm: add resource caps structure and api changes" 2019-07-12 02:20:32 -07:00
Dhaval Patel
d710ac7f11 disp: msm: sde: avoid duplicate fence create from client
SDE fence driver avoids duplicate fence creation if
fence timeline is not increased. This may lead to issue
if client closes the fence with failure ATOMIC_COMMIT.
SDE fence driver provides the closed fd node to subsequent
valid commit and leads to invalid state. This patch avoids
duplicate fence creation from crtc and connector object
instead of sde_fence.

Change-Id: Ic7b43762f0ad251fb20e42edb5f4d5f401790e14
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-07-10 11:15:23 -07:00
Shubhashree Dhar
50a191e13b disp: msm: sde: Correct initialization value for frame count
For calculating fps, correct frame count initialization
from 1 to 0 to avoid counting one extra frame on every
periodicity window.

Change-Id: I53cea321bb4d3335cc58e08df2f530cd1a306297
Signed-off-by: Shubhashree Dhar <dhar@codeaurora.org>
2019-07-09 22:39:31 -07:00
Nilaan Gunabalachandran
d92000cdd4 disp: msm: add resource caps structure and api changes
Create a data structure to maintain available hardware resources
and track capabilities. This data structure is used to send
the current available resources and caps information to
connector ops get_mode_info, get_modes and validate_mode to
process the display mode.

Change-Id: If38fc628ee5ab4729821f88c0050ab45375187b8
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-02 17:34:49 -04:00
qctecmdr
acf755573d Merge "disp: msm: dsi: DSI PHY V4 support of dynamic clock switch" 2019-06-27 03:34:31 -07:00
qctecmdr
13a11e75b0 Merge "disp: msm: sde: add snapshot of SDE from 4.14 to 4.19" 2019-06-13 11:29:00 -07:00
Samantha Tran
d009254fda disp: msm: sde: add snapshot of SDE from 4.14 to 4.19
This change takes a snapshot from 4.14 to 4.19 as of
commit 47d149c31967 ("drm/msm/sde: Add null pointer
sanity checks").

Change-Id: Ib40428c562c3561c8a20d9849f16d13151496005
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-06-05 13:18:21 -07:00
Yujun Zhang
39bc44163c disp: msm: dsi: unify dynamic clk support for command mode
Currently the dynamic bit clock switch trigger for command mode
is supported via sysfs node. This might lead to unnecessary
race conditions, when dsi driver is enabling the dsi bit clock
as part of commit and at the same time if bit rate change via
sysfs happens. So make the trigger happens via kernel mode set
call as done for video mode.

Change-Id: I17acb408d2b6dbd6fa41994e56262e31e43d088b
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
2019-06-05 16:06:36 +08:00
Yujun Zhang
b0f2e2222e disp: msm: dsi: add support for dsi dynamic clock switch
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. Also with dynamic dsi clock
switch feature coming into picture, now populate the supported
refresh rate as list instead of providing a range. Modify the
logic to enumerate all the modes in dsi driver, taking dynamic
bit clocks, resolutions and refresh rates into account.

Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
2019-06-05 16:06:27 +08:00
qctecmdr
371ccc78c2 Merge "disp: msm: sde: fix encoder parsing in atomic_check phase" 2019-06-04 06:15:13 -07:00
Veera Sundaram Sankaran
89511222a6 disp: msm: sde: fix encoder parsing in atomic_check phase
During atomic_check phase the encoder_mask is taken
from old crtc->state leading to wrong validation.
Fix it by taking the encoder_mask from new crtc state.

Change-Id: Ifcfc4bee887168d8208ffdafb1cf5ea4c4473796
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-06-03 15:46:36 -07:00
Lakshmi Narayana Kalavala
70486d209c disp: msm: sde: remove vblank cache logic
Userspace is not supposed to request vblank until crtc is enabled,
because drm framework rejects the request if crtc is not enabled.
Any vblank request prior to that need to be cached in the userspace.
Hence removing the cache logic from the downstream driver.

Change-Id: I78ceee331cba2d691f68fd649bd5cf33f7868e72
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-05-30 16:22:59 -07:00
Lakshmi Narayana Kalavala
9e17babe6a disp: msm: sde: turn off/on vblank callbacks as per crtc
Current sde driver allows vblank enable and wait requests
even after crtc is disabled which would eventually lead to
enable of irq and timeouts in caller context. This change fixes
it by updating vblank callback status as 'on' during crtc enable
and shutdowns vblank callbacks before crtc disable is complete.

Change-Id: I52b74f685107f4dc8c83305c28f23cdcb4747730
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-05-30 16:13:09 -07:00
qctecmdr
9c05197ef9 Merge "disp: msm: sde: use wr_ptr interrupt instead of ctl_start" 2019-05-24 09:38:19 -07:00