Sathyanarayanan Esakkiappan
fa1ddd5447
qcacmn: Trigger IRQ on Peregrine/swift by setting IRQ Bit of LF_TIMER 0
...
Set Interrupt bit of LF_TIMER 0 to induce interrupt on swift/peregrine
Change-Id: I8a3941262dd7a4b19f8734b4017c9293fbb1b981
2018-09-18 16:17:50 -07:00
Karunakar Dasineni
7b61c6ca74
qcacmn: WAR for CE status ring timer intr issue
...
Enable timer threshold interrupts for CE destination ring.
Change-Id: I851283a5ae6dc6d0f237aa90fdf401fd52794377
2017-06-12 17:19:24 -07:00
Venkateswara Swamy Bandaru
2aa2c6913e
qcacmn: regtable population of QCA8074
...
Added qca8074def.c that holds the register
table entries for qca8074.
Change-Id: I40b170722c2177cf5f53b5728cfae3730eeb8500
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org >
CRs-Fixed: 1042915
2016-09-20 20:25:39 +05:30
Venkateswara Swamy Bandaru
c5de4d9fd7
qcacmn: Cleanup target reg table
...
Remove unused fields in target reg table.
Change-Id: Ic183f7a27ffd5d4542dfe1c3eccb11825539c70f
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org >
CRs-Fixed: 1042915
2016-09-20 20:23:50 +05:30
Houston Hoffman
056d452238
qcacmn: Add check for supported register
...
Register offsets have 2 possible invalid values.
need to check for both values.
Change-Id: I6168aa46c4af66169284b98dee26ab56e4ed12c5
CRs-Fixed: 1012824
2016-05-19 18:00:33 -07:00
Houston Hoffman
c3c6bc1e5c
qcacmn: Add support for Regtable convergence
...
Add regtable definitions for chipsets AR6004,AR6320,AR900B,
AR9888,IPQ4019,QCA9888,QCA9984
Change-Id: Ic018a1396aa36f61ead6d8607feda4711e2a2b07
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org >
CRs-Fixed: 1009050
2016-05-19 17:59:43 -07:00
