Commit Graph

84 Commits

Author SHA1 Message Date
qctecmdr
1fc486ad3e Merge "disp: msm: sde: ctl hw flush ops clean up" 2020-03-21 13:08:07 -07:00
Narendra Muppalla
68ee65353b disp: msm: sde: align timing engine vsync based on panel vsync
This change adds logic to align timing engine vsync with panel
tear check if it is supported.

Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-03-11 10:14:57 -07:00
Dhaval Patel
9438f3448b disp: msm: sde: add underrun line count information
Add underrun line count information for each underrun.

Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-02-28 11:57:47 -08:00
Nilaan Gunabalachandran
f51424f8a7 disp: msm: sde: ctl hw flush ops clean up
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-02-25 14:18:59 -05:00
Narendra Muppalla
42a8aea8fc disp: msm: sde: add pm_qos support for cmd mode display
Add/remove pm_qos request during sde encoder resource
controller enable/disable for command mode display.

Change-Id: If3247eb215a58eaae3ee0b4c7a90e7f5254e690c
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-02-13 16:07:03 -08:00
Jayaprakash
f7d08feb38 disp: msm: sde: add enc_id check before decrement avail HW resources
Add changes to commit and decrement only those
hardware resources which are required for the modeset.

Timeline of Commit C1 with CWB modeset:
---> Atomic_check
	Primary encoder has allocated required HW resources.
 	CWB encoder has allocated required HW resources.
---> Atomic_commit
	On primary encoder, connector is seamless hence
	there is no virt_modeset call.
	On CWB encoder, there is virt_mode_set call
	and during commit HW blocks there is unconditional
	decrement for all the HW blocks with rsvp_nxt.

This change ensures hardware blocks are available during
dp display mode validations.

Change-Id: Ifd9439cfc96e727c3093af5f47802c8367775cd7
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-02-12 13:34:41 -08:00
Narendra Muppalla
f402d8e542 disp: msm: sde: program dither based on input data
This change programs dither based on user mode input data and
reprograms the dither when device comes out of power collapse.

Change-Id: I83be20c8eb2dc2221cc57cd2395f6512338ff6ef
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-02-10 15:33:42 -08:00
Abhijit Kulkarni
2c6c071e45 disp: msm: sde: move resource state change to display thread
In the current kernel version calling kthread_mod_delayed_work
in irq context is not allowed. Due to this resource control state
change to idle on frame done is handled in display thread context.

Change-Id: I709f7e04ac23d7dde72cea1c19d3767b6abc147e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-02-07 10:33:08 -08:00
qctecmdr
c89633ed36 Merge "disp: msm: add support for variable compression ratios" 2020-02-03 00:11:10 -08:00
qctecmdr
da7839e18e Merge "disp: msm: use iterator APIs to walk the connector list" 2020-01-30 17:35:51 -08:00
Abhinav Kumar
c4f5050e13 disp: msm: add VDC topology related changes
Add support to configure the DPU pipeline to support VDC-m
topologies.

Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
2020-01-29 13:45:35 -08:00
Abhijit Kulkarni
e2726c7b1a disp: msm: sde: allocate dsc block based on capability
Certain DSC hw blocks only support 444 mode, while others
support both 444 and 422 modes. This change adds support in
resource manager to check the hw resource requirement with
the capability of the block and then reserve the correct
hw resource.

Change-Id: If85beb2f2f25e9eb7f8a8321c94b57878d048369
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
d3d3f808d4 disp: msm: sde: use pp dsc api only if hw supports
This change checks the capabilities of pingpong block to
check if it needs to call the pingpong api to enable or
disable the dsc. Certain hw versions do not have support
in pingpong block to enable/disable the dsc instead the
dsc block itself have the hooks to control the DSC.

Change-Id: I17dd45479cc33ff2e81f6a6e5a5a8704562dfd24
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
acb8d98e66 disp: msm: use upstream dsc config data
This change enforces dp, dsi and the sde drivers to use the
drm framework defined dsc_config data structure. As a part of this,
it introduces the sde_dsc_helper API to configure the dsc params
and creating a PPS command. Earlier each driver implemented it's
private versions leading to duplication of code. Additionaly the
helper api supports DSC spec 1.2 422 and 420 mode.

Change-Id: I25933fab08cdabbc6787079926885d1a78945e97
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:24 -08:00
Abhijit Kulkarni
ac8ae6b85f disp: msm: sde: use dce api to configure dsc
This change introduces dce api to the encoder component to
configure supported compression hw. This allows encoder to
remain independent of the compression type and specification
supported by the hw.

Change-Id: I6bc35289495b05f57a83323cbab1ea14e9e15db0
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:33:14 -08:00
Abhijit Kulkarni
dc8e0291e4 disp: msm: sde: move dsc implementation to a new file
This change moves the DSC implementation into a separate file.
This is required to add support for new compression algorithms.
This cleanup change also, moves struct sde_encoder_virt
declaration to the encoder header file.

Change-Id: Idc3b96e65fcce2a7ee6e17af604cec0cb574f6f7
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:30:43 -08:00
Steve Cohen
8469b7be9e disp: msm: use iterator APIs to walk the connector list
Use the DRM APIs for walking the list of connectors. This ensures
the proper locks are taken to prevent possible corruption by other
threads.

Change-Id: Iacdd1c6ad8eab224ceac550e0229489851a09706
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-01-17 18:21:38 -05:00
Linux Build Service Account
8e2dde8420 Merge changes If37ec780,Ia691c95d into display-kernel.lnx.1.0
* changes:
  disp: msm: sde: remove sde wrapper for clock set flags
  Disp: Snapshot change for lahaina display driver
2019-12-04 17:27:51 -08:00
Yuan Zhao
6cb205cbba disp: msm: sde: migrated new sde icb bus scaling driver for lahaina
Migrate to icb framework API in drm and sde driver. And
also removes old msm_bus custom APIs from the driver.

Change-Id: Ifcf6d6f157594638075742fe328b29a9be065bca
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
2019-12-03 18:46:27 -08:00
Narendra Muppalla
d1d9ae8b19 Disp: Snapshot change for lahaina display driver
This snapshot change adds downstream support
for drm 5.x+(msm_lahaina branch) linux kernel.

Change-Id: Ia691c95da155a00e449c91a2f1a5b20a8e71aed4
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-11-24 12:30:51 -08:00
qctecmdr
b269dd05bc Merge "disp: msm: sde: fix video mode prefill lines for RSCC" 2019-11-02 09:08:46 -07:00
qctecmdr
7139bedc5a Merge "disp: msm: sde: Use platform independent API for 64-bit div" 2019-11-02 06:58:12 -07:00
Veera Sundaram Sankaran
b1c9d65e3d disp: msm: sde: fix video mode prefill lines for RSCC
The RSCC static wakeup and the bandwidth trigger for
the downvotes are based on the prefill lines. Reduce
the prefill lines based on the panel vertical front
porch to avoid issuing bw downvotes during active
region of the previous frame.

Change-Id: I408209ba308c32e71d9f70c5ed7e60c134877c84
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-11-01 10:09:35 -07:00
Ravikanth Tuniki
b0df721f2d disp: msm: sde: Use platform independent API for 64-bit div
64-bit division( operator "/") on 32-bit platforms is not supported.
Using platform independent API's here.

Change-Id: I1ec71ac120bb29b7f0bceed581b979606f81e2a5
Signed-off-by: Ravikanth Tuniki <rtunik@codeaurora.org>
2019-10-31 15:38:00 +05:30
qctecmdr
ee16fbb03f Merge "disp: msm: sde: update avr mode config during commit prepare" 2019-10-24 21:31:57 -07:00
Veera Sundaram Sankaran
6cdd1f1fe0 disp: msm: sde: avoid encoder power-collapse with pending frames
The encoder idle work is scheduled during the frame-done event
to be executed after a timeout. During the execution, the check
for any on-going/pending frames is invalid as it checks for > 1.
Fix it to check for any non-zero frame-pending and avoid
power-collapse.

Change-Id: If7715ee56cc9bfa63787811458f4fc91de540013
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-10-21 13:32:24 -07:00
Jayaprakash
aad3dd4525 disp: msm: sde: update avr mode config during commit prepare
Add changes to support avr mode config update during
prepare commit which happens before gpu fence wait
for the input buffers.

Change-Id: Ib2cb5b7e1f10501914c003f6cf066b85048f79d4
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-18 12:53:56 +05:30
Veera Sundaram Sankaran
fb54f6e6e7 disp: msm: sde: switch to WD vsync on unexpected panel jitter
Switch to watchdog vsync whenever panel jitter is
identified during frame-transfer on command mode display.
This would allow the HW to finish processing the frame
with watchdog vsync source. Switch back to default vsync
source after the frame-transfer is complete. This would
help in the MDP hang issues in panels that generate TEs
with thresholds greater than the projected jitter.

Change-Id: Ic3fa78d90e7f44cb0186857716ac27e72505fd32
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-10-01 13:32:42 -07:00
Jayaprakash
7ba937c3ea disp: msm: sde: add null check for pingpong hw block
Add null check before accessing pingpong hw block
allocated during mode set to physical encoder.

Change-Id: Ic464e7c7087f280b1198f6b7485bc0763322c532
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-09-27 14:17:20 +05:30
qctecmdr
8d3febc8a0 Merge "disp: msm: sde: ensure input handler unregistration in command mode" 2019-09-18 12:10:25 -07:00
Veera Sundaram Sankaran
4776221d5b disp: msm: sde: fix panel mode check during SUI validations
During SUI validations and transitions, the encoders
are iterated to find the panel-mode. If concurrent
writeback is enabled, it is assumed as video mode.
Add check to consider only the built-in display
panel mode during sui to avoid wrong interpretation.

Change-Id: I2901eb29a0799571a95f6ab6f9f3f2c6154424c5
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-09-12 13:56:30 -07:00
Lei Chen
e50cce2dfe disp: msm: sde: ensure input handler unregistration in command mode
Input handler is only registered in command mode, so add this change
to ensure that the input handler will be only unregistered in command
mode.

Change-Id: I15f652439339eee45b0ed3c011aa2922151f68ba
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2019-09-10 14:58:57 +08:00
Dhaval Patel
6f06e5cd6f disp: msm: sde: wait for specific pp_done instead of zero
2 Frames transfer pending is possible with posted start.
One ongoing frame and another triggered frame. Current SW
waits for pp_done interrupt if pending frame count is greater
than 1. It is possible that interrupt may be missed for ongoing
frame. In that case, SW should run pp_done wait for one by one
frame instead of two frames together. It allows encoder to
check the ctl scheduler status and trigger the frame done
event on time.

Change-Id: I4817842292d96747890ee70da8a5bdf9b56816ed
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-20 21:12:52 -07:00
qctecmdr
2f41e9ab66 Merge "disp: msm: sde: ensure LUTDMA is complete when auto-refresh enable" 2019-08-13 21:01:42 -07:00
Jayaprakash
527692f6f4 disp: msm: sde: ensure LUTDMA is complete when auto-refresh enable
Currently LUTDMA kickoff is immediately followed by CTL flush,
immaterial of the LUTDMA DONE status in command mode. If LUTDMA
kickoff happens too close to the read_ptr in auto-refresh case, it might
cause a race condition between LUTDMA & CTL flush, due to a HW issue.
Serialize LUTDMA & CTL flush by making the LUTDMA kickoff as blocking
to avoid the race condition in auto-refresh case similar to video mode.

Change-Id: I4f4ae90a2c4f1bc8a0686d8fd4f8aa439123c531
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-08-08 18:02:23 +05:30
Veera Sundaram Sankaran
5a2dfc1e83 disp: msm: sde: fix release fence signaling in error cases
Handle release fence/frame-done error signalling for
error case like esd failure, pp_done timeout, interrupt
disable on cpu, etc. It fixes the race condition for
pending_frame count update and also triggers correct
wait function for wr_ptr wait failure.

Change-Id: Iad08f20592c97221a1626bb40e607c398a9812b6
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-08-07 18:56:47 -07:00
qctecmdr
2a75326609 Merge "disp: msm: sde: Add event log for uidle veto enable" 2019-07-27 03:47:20 -07:00
qctecmdr
bc91692047 Merge "disp: msm: sde: avoid input handler of registration in video mode" 2019-07-26 09:14:09 -07:00
Lei Chen
92fe6638ed disp: msm: sde: avoid input handler of registration in video mode
Input handler is used for early wakeup DSI and MDP clocks from
idle power collapse. DSI clock won't be disabled in video mode
during idle power collapse, so the input hanlder isn't needed
for video mode.
This change avoids the input handler to be registered in
video mode.

Change-Id: Id23bad192b6671126978d707db464e7aaee1c77f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2019-07-24 09:33:35 +08:00
Nilaan Gunabalachandran
1e06ddddc3 disp: msm: sde: Add event log for uidle veto enable
Print uidle status fal10 enable bit as part of checking status.

Change-Id: Ibe00216ac22bb31fbe0925db3abc1d5dc4371ad3
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-23 16:22:16 -04:00
qctecmdr
3588284310 Merge "disp: msm: sde: fix cwb, dp and wb tear down sequence" 2019-07-22 11:52:53 -07:00
Dhaval Patel
bcd97aa368 disp: msm: sde: fix cwb, dp and wb tear down sequence
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.

Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-07-18 14:13:33 -07:00
qctecmdr
3ab9638e45 Merge "disp: msm: add resource caps structure and api changes" 2019-07-12 02:20:32 -07:00
qctecmdr
e3be8e7636 Merge "disp: msm: sde: Ensure that dirty dsc blocks are flushed properly" 2019-07-11 22:21:44 -07:00
qctecmdr
751cbf5570 Merge "disp: msm: sde: avoid connector state mode update" 2019-07-05 21:36:26 -07:00
Dhaval Patel
10d925633a disp: msm: sde: avoid false error for encoder restore
Below sequence can trigger encoder restore failure due
to cur_master unavailability.
 -> Primary encoder is attached to crtc-0
 -> Primary encoder enters in power collapse state
 -> CWB encoder attached to crtc-0
 -> Atomic_check updates the crtc encoder_mask with
    two encoders.
 -> Prepare_commit triggers power restore
 -> crtc triggers encoder_restore based on encoder_mask

CWB encoder is not enabled at this stage and it will fail
to restore. This patch avoids the error message in this
valid condition.
2019-07-03 11:02:44 -07:00
Nilaan Gunabalachandran
d92000cdd4 disp: msm: add resource caps structure and api changes
Create a data structure to maintain available hardware resources
and track capabilities. This data structure is used to send
the current available resources and caps information to
connector ops get_mode_info, get_modes and validate_mode to
process the display mode.

Change-Id: If38fc628ee5ab4729821f88c0050ab45375187b8
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2019-07-02 17:34:49 -04:00
Abhijit Kulkarni
dcea657cce disp: msm: sde: avoid connector state mode update
There is a race condition between sdm thread and display thread, when
sdm thread may be accessing the mode_info field while duplicating the
connector state, display thread may be updating the current mode info.
This would lead to the next commit using invalid mode and could cause
wrong hw configuration.
This change removes copying the mode_info in encoder struct while
atomic check phase and also removes accessing the connector mode_info
during mode_set. The encoder struct is now updated at the mode_set
with the cached connector mode.

Change-Id: I069ed592ec017ce4aa5c9c94b340bf94c5e1ebff
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-07-02 12:57:31 -07:00
qctecmdr
d2ffb846ba Merge "disp: msm: sde: reset ctl during wr_ptr_irq timeout" 2019-06-28 04:27:31 -07:00
qctecmdr
8d38e0fb46 Merge "disp: msm: fix vsync wait for poms and dms" 2019-06-27 05:57:07 -07:00