In hal_delayed_reg_write change the order of
hal_is_reg_write_tput_level_high and pld_is_device_awake check. This
ensures that throughput level is checked before checking for device
wake state. This is beneficial in saving CPU cycles in high throughput
scenarios.
Change-Id: I23d0bde46779df9dca4388bf67c9395999274f3a
CRs-Fixed: 3078096
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
Currently reg work is being cancelled in deinit path,
cancel work will remove all the pending work items
and wait for completion of current executing work.
But in reg work case even pending work items has to be
executed because we don't want to skip HP/TP values update.
To avoid this make sure all the pending reg work items are
flushed then disable the work for further queueing.
Change-Id: I2ba1e26cf41fb3b0c33ec584c56525cbfac94d8f
CRs-Fixed: 3065038
Add API to get dp peer authorize state.
Also modify dp_tx_get_rbm_id_li to update rbm for IPA offload
scenario
Change-Id: I0f8cca4623a1c3b840f336aa6d67740951cb6700
This FEATURE_HAL_DELAYED_REG_WRITE_V2 was added to fix the
Audio jank issue, but it could not resolve it completely,
so that was later fixed by existing delayed reg write
support with the help of SMP2P messages to communicate
with FW regarding PCIe link status. This code is not being
used, so removing it and cleaning up the redundant code.
Change-Id: Iada088e72a76b4c071c8a80ee945f36ac959670e
CRs-Fixed: 3056475
Initialize the last_desc_cleared pointer to -1 not 0, and
also fix the check it should always behind tp.
Change-Id: I281e066d45a99ac99d4f3c4e0bcc3f65f14bb589
CRs-Fixed: 2987029
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
hal_reg_write_need_delay is invoked immediately after
q_elem->valid check. The first two instructions in
hal_reg_write_need_delay could be in the CPU instruction
pipeline which could result in possible loading and
dereferencing of NULL srng from an invalid q_elem.
Fix is to invoke hal_reg_write_need_delay just before
hal_process_reg_write_q_elem and also add NULL checks
to avoid the srng NULL pointer dereference.
Change-Id: I2de50b1e78782e3c91a9cb4477f28d91f9c29439
CRs-Fixed: 2973257
Return LMAC start id also as part of hal_get_meminfo API.
This field is added to hal_mem_info struct.
Change-Id: I013d357cf4337702c06a91ed15e8337469865270
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Introduce intermediate EP voting state during this transition state
access the votes only if direct writes are not possible.
Change-Id: Ib4522aef2209b4797100ca84e4e230a00e14b654
CRs-Fixed: 2954903
Even though HP/TP updates are posted writes at CPU level, they
are getting blocked until soc comes out retention which is hogging
CPU.
To avoid this if EP is in low power state update HP/TP writes from
delayed work context. In delayed work vote for EP awake wait till it
comes out low power state and then proceed to HP/TP update.
Change-Id: I61d5795f58f25f850b5a9ad4d30e3181dba23713
CRs-Fixed: 2913495
Add support to update CE srngs HP/TP in delayed manner
for QCA6750 target. This avoids busy wait in register update.
Change-Id: Id825a6fdf709187765ff823cb3015db21a024af3
CRs-Fixed: 2894094
For the minidump feature, the wlan_minidump_remove function
definition is modified. So, update the function parameters
accordingly at all instances of the wlan_minidump_remove function.
Change-Id: I5a346f6cdf423ece02fb08d68e4422251af54876
CRs-Fixed: 2860435
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
WLAN HW can still access the IPA tx doorbell address post
disable pipes if there are any pending tx completions which
could result in a NOC error.
Fix is to reset the WBM2SW ring HP addr to shadow addr in
DDR before pipes are disabled.
Change-Id: I52900eb34530388487923a887354ef8839d8c728
CRs-Fixed: 2846421
Currently, we decrement active_work_cnt in a while loop in delayed
register worker and later on make a "allow_l1" call to enable L1ss.
The bus suspend routine depends on the value of active_work_cnt to
determine if any register writes are pending. In case there are, bus
suspend is rejected.
As a result its possible that when bus suspend happens, the
delayed worker while processing the last remaining enqueued
write, makes the active_work_cnt to 0. This will allow the bus suspend
routine to continue to disable the bus, even before the
delayed-reg-worker has called allow_l1 and run to completion. This may
lead to a NOC error while calling "allow_l1" API from
delayed-reg-worker.
Hence, move the decrement of active_work_cnt to the very end in
hal_reg_write_work function.
Change-Id: Iec602f97c953df1c6a018310fd02ab458547ce3a
CRs-fixed: 2813733
This change fixed compilation error about implicit-fallthrough and
pointer to in cast.
Change-Id: Iea2c25d97d8a039ed0f8083078427a8f8de70cd1
CRs-Fixed: 2814658
Delayed register write work needs to be flushed before bus suspend to
make sure there are on pending writes after driver's bus suspend routine
exits. In case delayed work context is not able to finish before the bus
(PCI) is suspended (DRV), it may lead to a NOC error.
Change-Id: I40cbcec5d23ddd75ec87aed69ac45d95510fa880
CRs-Fixed: 2813733
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
Configure low threshold for monitor ring only when monitor
vap is created. This is needed to avoid spurious low threshold
interrupts on monitor ring since the low threshold condition always
evaluates to true.
Change-Id: I452c0ada84e0a4f18e410c865d8a6a7f50329aef
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
make sure both PCIe and device are force woken for the register
writes for hsp, or write may fail.
Earlier WAR is not required as we have root caused it.
Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b
CRs-Fixed: 2677342
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
The delayed register write enqueue fills a queue element
with the required data which can be dequeued in a workqueue
running on a different CPU. Since these operations are not
lock protected, there can be stale value access when memory
write has not been flushed to the actual address.
Using write memory barrier before setting the valid flag for
a queue element will make sure that the dequeuing worker
thread will always see the updated values if the element valid
flag is set and thereby avoid any race condition.
Change-Id: I81b0735f0fb39599095ad309157020c691e25a0b
CRs-Fixed: 2665576
The delayed register write for srngs will have
the value of the HP/TP at the time of enqueue,
but the final value which is written to the
hp_addr/tp_addr will be determined based on
HP/TP value at the time of dequeue of the
entry for a particular srng.
Hence to know what was the exact value which
was written to the HP/TP address, add one more
element in the delayed register write entry.
This element will contain the value of the
HP/TP which was actually written to the address.
Change-Id: I73e592611fa50b106da1deda06b839cf4fbe2126
CRs-Fixed: 2658331
As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.
Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).
Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Build failure happen when use the incorrect print format for
pointer. The timer type should not be used for time difference.
Use %pK for pointer format, and change the variable type to
uint64_t for delta_us.
Change-Id: I7da553ee2a770e4498a23f16d5187dec74357635
CRs-Fixed: 2639868
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
Handle minidump logging using dynamic
configurablity options. Data structures
to be logged in minidump can be configured
using internal INI file.
Change-Id: I99f12b3f98c4a9c0e15c3e5d611019e6b8d0909a
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
