Delay write of SRNG regs may happen on different CPUs.
Sometimes wmb may not sufficient to protect the update
in sequence.
So to fix update issue sleep and retry before checking
again for update.
CRs-Fixed: 3717683
Change-Id: I6c7916f91ecefa8175d3e3d9108d018fc8a42cfc
Ring IPA TX doorbell with HW HP value to avoid out-of-sync
scenarios between WLAN and IPA after IPA pipes are disabled
and then re-enabled.
CRs-Fixed: 3479426
Change-Id: Ia88c0228759e241722fe31fd1a252e70484684e9
Delay write of SRNG regs may happen on different CPUs.
Sometimes wmb may not sufficient to protect the update
in sequence. Change is aimed to buy more time for the
update of different CPUs.
Change-Id: I4149decf5a29ea213aa38abd2bef062f25d7858d
CRs-Fixed: 3591457
ring history array size is large. Change is aimed
to split the allocation into small trunks to avoid
memory allocation failure.
Change-Id: If977baab23718d0186ad2ce6d33319b52096f2f9
CRs-Fixed: 3479226
1. Check Tx halt during umac reset and avoid halt if set already.
2. Perform SRNG disable only in case of umac reset
Change-Id: Id364a6460a64e83002b5c96e08031ad2a0bc8fd7
CRs-Fixed: 3459427
Add srng pointer register writing history, it is helpful
for debugging srng HP/TP update issue from host side.
(1) if host faced UMAC source ring, record the HP value and timestamp
when host write the register.
(2) if host faced UMAC destination ring, record the TP value and
timestamp when host write the register.
Change-Id: Ib98e48e1d32defb0d8b30b854b5b0c23691cca59
CRs-Fixed: 3427908
At continuous physical address limited telematics platform,
in order to avoid occasional memory alloc failure with big
kzalloc size, it's better to use virtual memory allocation
API instead. And below items will be refined to replace
malloc with valloc if CONFIG_ENABLE_VALLOC_REPLACE_MALLOC=y.
1 x 30488 = 30488B @dp_soc_attach:15189
1 x 52096 = 52096B @hal_attach:1104
4096 x 64 = 262144B @dp_rx_desc_pool_alloc:337
Change-Id: I57a6f78f690b5be1838de954933ae36129cea234
CRs-Fixed: 3426935
Support REO2SW ring pointer update threshold configuration,
it is helpful for PCIe utilization improvement.
timer based threshold - M: issue pointer updates when M micro
seconds has elapsed.
number based threshold - N: issue pointer updates when N entries
updates occur.
Change-Id: I49ed388520fd52e97e303d6ea9c04ced6cb5cf5f
CRs-Fixed: 3420101
The kernel-doc script identified a number of kernel-doc issues in the
hal/wifi3.0 folder, so fix them.
Note that there are a number of instances where public functions have
their implementation documented in addition to having their interface
documented, so remove the duplicate documentation since only the
interfaces should be documented.
Change-Id: Ic238c0f53658e8754882c83204ffae5ad713ec6b
CRs-Fixed: 3410624
change allocation location for reo qref table.
per probe allocation results in mem alloc failure when
frame is fragmented
Change-Id: I5922bddebcd0577ba38734ae7d4194d726d825aa
CRs-Fixed: 3326520
Current code does not use the SSR host log collection API.
Fix this by adding SSR host log collection API usage.
Change-Id: I9dfb0bd7054986760a711d0752f37f4327c706b2
CRs-Fixed: 3339933
Add changes to move ioremap of PMM SCRATCH register outside
interrupt context, as ioremap in interrupt context in not valid.
Change-Id: I0fa645c55e10a5241011a1f4ffdccdca48c50d29
CRs-Fixed: 3371194
In case of memory allocation failures,
return appropriate failure to the caller in hal attach.
Change-Id: Ifc319bbc274d8a13836968d460eb8067857363b8
CRs-Fixed: 3357203
REO module may hang when REO commands are queued after WoW enable WMI
sent to FW. Change is used to check WoW progress before accessing REO
CMD ring. If WoW is in progress, then defer REO commands.
Change-Id: I9cd8390e77ef33f98f84cb604f152e3f9a0e4203
CRs-Fixed: 3362608
Retain ds ring indices across wifi restart to avoid
edma hang. Fetch the indices from ds module and set
the corresponding ds ring indices.
Change-Id: Ia299a7006166aef096c7d2c1f65f6bef65415a37
CRs-Fixed: 3332152
Below signature is seen on sdxpinn when HOST reads IPA TX
doorbell address, which leads to HLOS crash.
Internal error: synchronous external abort: 96000010
Indeed IPA TX doorbell address is write-only. Behaviors
on such read access violation is arch-dependent. On
certains platforms, such violation is ignored but read
returns 0.
Hence remove the read access to IPA TX doorbell address
in hal_srng_dst_init_hp() to avoid arch-dependent
behavior.
Change-Id: I3486cd81741922e697e2b3d307db3209b710aa6a
CRs-Fixed: 3339302
1. Changes to get correct write address in hal_get_window_address_5332.
2. Fix for monitor init crash - Added dummy entries to match the
ring_id.
Change-Id: If59b1c231d4595a95e7c1f02de1dbe0ce27a8805
CRs-Fixed: 3268933
When FW was enabling WOW, a ring HP update interrupt is seen
which led to fw crash.
This change records any PCI writes that went through during
runtime suspend from host.
Change-Id: I3c44760ebaf49a131b483813522fe3e451957215
CRs-Fixed: 3280166
For Beryllium LMAC rings, hal_get_srng_ring_id() provides the ring IDs
separately per each LMAC only if that LMAC ring is a destination ring
(This is done to use a common source ring for the DMAC rings).
But the ring IDs for LMAC source rings like DIR_BUF_RX_SRC_DMA_RING are not
being provided separately per LMAC. As a result, these ring IDs in
split-PHY mode are colliding for the 2 LMACs.
Fix this by doing the following.
- Mark the DMAC common rings within the LMAC rings.
- Provide ring ID separately per each LMAC if the ring is an LMAC ring
but not a DMAC common ring.
Change-Id: Ifdae085b5784a03763abfc4edb42d94593e3ea21
CRs-Fixed: 3282702
Hal layer changes to handle Umac post reset
and post reset complete events from firmware.
Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222
Add support to track the high watermark for the number
of entries which are used at any given instant. This helps
in identifying if the ring size is sufficient or is being
full for certain use-cases.
Change-Id: Id3ffa52c653696699fbcfbb556a815d5f7908863
CRs-Fixed: 3235115
Move the function attribute to common file so that the
parsing issue due to unreferenced tcl_data_cmd can be
fixed on other targets also.
Change-Id: I40a7196926061e8d232f0f070c0ed045dafd97e2
CRs-Fixed: 3228562
With restructuring in HIF runtime PM module, modules are
required to register with the HIF runtime PM module. Also,
changes are done in functions of allowing and preventing
runtime PM suspend as part of restructuring.
This change registers DP, HTC and HAL internal modules
with runtime PM module and update HIF runtime PM function
calls with the restructured code of HIF runtime PM module.
Change-Id: I8899a1d3b92a90a05c5eaf4df7609f4008f739f8
CRs-Fixed: 3169372
For reo_cmd ring, in current implementation, we call hal_srng_access_end
in case a descriptor is not available before baling out. This may cause
a write to the shadow register for the reo_cmd ring. In case we are in
the middle of WOW, this can be problematic.
Modify existing implementation to use hal_srng_access_end_reap, which
will not schedule a write to the register and simply return.
Change-Id: Ifb83d904e39b3d749522cd246a5ab3fe51a3104e
CRs-Fixed: 3194289
Shadow config v2 can support max of 36 shadow
registers only. For KIWI target, there are 40
shadow registers supported.
Hence add support to send shadow config v3
for KIWI.
Change-Id: If57e6597397da3e239f25a6c0cc24f8fd37dcdf1
CRs-Fixed: 3167758
Flush and invalidation of descriptor memory at allocation is helping
to avoid NULL descriptors issues in TX and RX path.
Change-Id: Ifcdb65df01365e7ec0b0be59d8b4bf862d90943d
CRs-Fixed: 3180696
In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
For Kiwi, if UMAC force wake is enabled, HIF window register
support is needed as well. currently hal_soc->init_phase just be
true for a very short periord, this lead to hif_force_wake_request
is called frequently when configure register during initialization,
this is not necessary as pld and device is not in power collapse
state during this period.
Enable HIF window register and increase init_phase true period
Change-Id: I0b5394bbc1ca73d20b2fcabbf2a261e6f8335626
CRs-Fixed: 3097991
Use the tracepoints to trace delayed register write, ce
tasklet scheduling latency, tx, and rx packets.
Change-Id: I63a89276177a9d0466dcb0c831eeb8e938a2bf79
CRs-Fixed: 3081870
In hal_delayed_reg_write change the order of
hal_is_reg_write_tput_level_high and pld_is_device_awake check. This
ensures that throughput level is checked before checking for device
wake state. This is beneficial in saving CPU cycles in high throughput
scenarios.
Change-Id: I23d0bde46779df9dca4388bf67c9395999274f3a
CRs-Fixed: 3078096
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
Currently reg work is being cancelled in deinit path,
cancel work will remove all the pending work items
and wait for completion of current executing work.
But in reg work case even pending work items has to be
executed because we don't want to skip HP/TP values update.
To avoid this make sure all the pending reg work items are
flushed then disable the work for further queueing.
Change-Id: I2ba1e26cf41fb3b0c33ec584c56525cbfac94d8f
CRs-Fixed: 3065038
