samsung-sm8650/android_kernel_samsung_sm8650-modules
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06e90b5374beddeb50a9a50049b8ec94150d71ea
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10 Commits

Author SHA1 Message Date
Venkateswara Naralasetty
06e90b5374 qcacmn: Add default register values for WCN6450 
Add default register values required for WCN6450.

Change-Id: I47880e95cb101ad145d4e750e8811a0153b19482
CRs-Fixed: 3381090
 2023-01-20 01:35:27 -08:00
Hariharan Ramanathan
f75a30225c qcacmn: Add changes to move ioremap outside interrupt context 
Add changes to move ioremap of PMM SCRATCH register outside
interrupt context, as ioremap in interrupt context in not valid.

Change-Id: I0fa645c55e10a5241011a1f4ffdccdca48c50d29
CRs-Fixed: 3371194
 2023-01-10 05:32:28 -08:00
Hariharan Ramanathan
433a137917 qcacmn: HIF changes for QCA5332 
1. Changes to support cmem write for AHB devices.
2. Interrupt enablement issue - Incorrect CE address was given which is
fixed.
3. dp_soc_init failure - dev_base_addr of Miami was NULL, which is
fixed.
4. Missing interrupt error logs - Added dummy entires for missing
interrupt in DTS and changes to support shared IRQ in wifi-drivers

Change-Id: I00e7666b2b978c35b5ccec5da21bf442ed0a7998
CRs-Fixed: 3268936
 2022-09-13 16:46:32 -07:00
Basamma Yakkanahalli
c0b1d0ebf0 qcacmn: use distinct I/O remap to access CE register for ipq5018 
In ipq5018 CE registers(0x08400000)  kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.

Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
 2020-05-18 22:33:42 -07:00
Sathyanarayanan Esakkiappan
fa1ddd5447 qcacmn: Trigger IRQ on Peregrine/swift by setting IRQ Bit of LF_TIMER 0 
Set Interrupt bit of LF_TIMER 0 to induce interrupt on swift/peregrine

Change-Id: I8a3941262dd7a4b19f8734b4017c9293fbb1b981
 2018-09-18 16:17:50 -07:00
Karunakar Dasineni
7b61c6ca74 qcacmn: WAR for CE status ring timer intr issue 
Enable timer threshold interrupts for CE destination ring.

Change-Id: I851283a5ae6dc6d0f237aa90fdf401fd52794377
 2017-06-12 17:19:24 -07:00
Venkateswara Swamy Bandaru
2aa2c6913e qcacmn: regtable population of QCA8074 
Added qca8074def.c that holds the register
table entries for qca8074.

Change-Id: I40b170722c2177cf5f53b5728cfae3730eeb8500
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1042915
 2016-09-20 20:25:39 +05:30
Venkateswara Swamy Bandaru
c5de4d9fd7 qcacmn: Cleanup target reg table 
Remove unused fields in target reg table.

Change-Id: Ic183f7a27ffd5d4542dfe1c3eccb11825539c70f
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1042915
 2016-09-20 20:23:50 +05:30
Houston Hoffman
056d452238 qcacmn: Add check for supported register 
Register offsets have 2 possible invalid values.
need to check for both values.

Change-Id: I6168aa46c4af66169284b98dee26ab56e4ed12c5
CRs-Fixed: 1012824
 2016-05-19 18:00:33 -07:00
Houston Hoffman
c3c6bc1e5c qcacmn: Add support for Regtable convergence 
Add regtable definitions for chipsets AR6004,AR6320,AR900B,
      AR9888,IPQ4019,QCA9888,QCA9984

Change-Id: Ic018a1396aa36f61ead6d8607feda4711e2a2b07
Acked-by: Venkateswara Swamy Bandaru <vbandaru@codeaurora.org>
CRs-Fixed: 1009050
 2016-05-19 17:59:43 -07:00