Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
In split link usecase with single DSI and dual sublink, the
pixel clock rate should be calculated based on effective lanes
rather than cumulative lanes on that DSI PHY. This effective lanes
can be expressed as number of lanes being used per sublink.
Change-Id: Ia534e816cc64b62c5fe0b9fcaabb9ba52d05bab0
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.
Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.
Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Currently when RFI is used on a video mode panel the horizontal or
vertical front porch values can be adjusted to maintain a constant FPS.
When this feature is enabled, driver is not propagating the new
htotal or vtotal values to usermode for accurate BW and MDP clock
calculation, which may lead to underrun in some usecase.
This change publishes beforehand all the RFI related timing
such as compensation type, hfp or vfp and clock values for
each mode for accurate BW and clock calculation.
Change-Id: Ib89c5e318fe978b0ae2215dedc430e057a9a81b9
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Some panels may require that the DSI link returns to the low-power
stop state (LP11) after transmission of every line. If a panel
requires that the DSI link returns to LP11, apply the LP11
insertion between lines feature.
This change adds support to
- Disable the command mdp burst mode
- Enable mdp idle ctrl
- Program the No. of dsi pclk cycles of idle time to
insert between command mode mdp packets. The idle time
must be long enough to cover the time link takes to
switch between HS to LP11 mode.
Change-Id: Ie718d334f05ce6c1ecd1a05b379bbbe18dec6330
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Clock lane can enter ino ULPS mode only in DPHY mode. For
CPHY, did not need to check the clock lane status for ULPS.
Change-Id: Iceddd8064ec75ce26613469cfb1bde36e883f865
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
For higher refresh, to provide higher transfer time we need to disable
RSC solver in MDP. This can be configured through the panel timing node
devicetree property. This change adds the parsing of the devicetree
property.
Change-Id: I9e708325da35086d2f955cbcc80bb164ccb116cd
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The order of the panel timing nodes specified in the device tree is
not guaranteed to be the same while being parsed in the driver. This
results in unintended modes being set as preferred timing mode. The change
introduces cell-index property, so that the timing modes can be
accurately indexed and parsed.
Change-Id: I8ccd4d5a15643bfe72bc8be084f5e91fac26feb4
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change adds support for enabling splitlink sublinks video data swap.
Change-Id: I731b85a5e8fe8638005433819957dd0658f72963
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Currently, RFI feature only supports panel that contains
a single timing node. This limits the feature availability
for panel with multiple modes or with DFPS support.
This change adds support for RFI on panels that contains
multiple timing nodes.
Change-Id: I3a7aadf7b6da3518350b2eb815602b13b5c259f5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Change removes the use of custom MSM DSI flags that will not be
available as part of GKI.2.0
Change-Id: I2337a54b1d6346ebdc18e9e6c3c8e7a07f421bdd
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update panel commands to support panel operating mode switch in
one timing node.
Change-Id: Ieb8303cebe78c699dfd5f274830418e87655ff56
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Expose panel mode from kernel to SDM with SDE connector property
CONNECTOR_PROP_MODE_INFO and set panel mode from SDM to kernel
with SDE connector property CONNECTOR_PROP_SET_PANEL_MODE for
avoiding private change in upstream code in QGKI kernel.
Change-Id: I0629dad9399967cc1118ac02ce30597076ca367d
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.
Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The change adds a new mode property allowed_mode_switch. The new
property is a 32bit bitmask that indicates the modes each mode
can switch to. This change is required to pass the driver mode
switching capabilities, so that user mode can reject any mode switch
that is not supported by the driver.
Change-Id: I76d1733a07a6d57487ba9f461055270d7e60e060
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
During clock switch, Pll delay is calculated considering escape
clock to be in KHz. But escape clock is in Hz. This leads to wrong
pll delay calculation.
Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
The change allows for configuring a command DMA window during which
the command is triggered. The DMA window must not intersect with the
MDP tear check window. Once the command transfer is successful, the
trigger control needs to reset to the default DMA trigger specified
by the panel.
Change-Id: I5485ca1f8e141ed92dc8c77c2daf579634271022
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
If the command line timing is given, select corresponding
drm display mode as preferred mode. Select first sub mode of
that timing as preferred mode if dynamic clock or dynamic fps
is enabled.
Change-Id: I688b3bc07f79f4d014b8a7797204d3d6a873222d
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Add support to read cphy boolean flag from panel dtsi
and configure DSI PHY registers accordingly. Update the
bit/byte clock calculation according to cphy specifications.
Update clock parents so that the relevant divider blocks
are configured to support cphy.
Change-Id: Iaca61eec01a488657b086f59910c52f8c79e26a4
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
In order to make dsi panel and dsi2hdmi panel compatible,
delete "qcom,panel-force-clock-lane-hs" property in phy and
use display panel's force_clk_lane_hs property.
Change-Id: I490e08b2ee859797c2b3aeddf109a3a4286fb922
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change removes scaling for porches while calculating h_total, as
it is not necessary. Using scaling for porches results in lower
clocks which in turn can lead to low FPS.
Change-Id: Idbad83e1c56f079e60fe5ac342f8dd977db54f8f
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
From Lahaina onwards, for compressed DSI output, widebus should be enabled.
In widebus mode, 6 bytes of data are transmitted per pclk.
For uncompressed output, widebus must be disabled to transmit 3 bytes
of uncompressed data per pclk.
Change-Id: I7fc0bdb2e1678152d57b4cbb8295063a2ba8ae73
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
There is lag or lead in the FPS during dynamic clock change,
along with the increment or decrement in clock. So, HFP or
VFP are adjusted to ensure a constant FPS.
Change-Id: I87ba7a185104a0f5f1d13734a7e487e728d6b2c0
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add a generic API which calculates the horizontal timings based
on the compression type in case compression is enabled and even
for non-compression cases.
Replace the usage of the DSC macros with this generic API.
Change-Id: Ie9174c20adc51a0be7c9127529d41faa4b473b55
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Add support for parsing VDC-m DTSI parameters and also
perform basic validation checks on those.
Change-Id: I4b13cf04b1500c3c801c227658cb787bdad6174f
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Change adds flag to identify dynamic mode switch with same
resolution and different fps. Block sending PPS command
if we hit this scenario, this optimizes mode switch time.
Change-Id: If5c86084cde641952fe294b512e937cfd1bb5479
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Adding debug, info and error prefix for log messages
in dsi files. To enable debug logs
run "echo 0x1 > /sys/module/drm/parameters/debug"
Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. Also with dynamic dsi clock
switch feature coming into picture, now populate the supported
refresh rate as list instead of providing a range. Modify the
logic to enumerate all the modes in dsi driver, taking dynamic
bit clocks, resolutions and refresh rates into account.
Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change ports the missing changes from 4.14 to 4.19
that were missed. It includes changes up until
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").
Change-Id: Idfdfe891f146e389e3c65cc3fc4c98d93220e789
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add support to selectively enable clock gating for supported
DSI clocks using a new debugfs node - config_clk_gating. This
new node would be created for every display node. See below
for usage examples:
To enable clock gating only for BYTE clock:
echo 1 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for PIXEL clock:
echo 2 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for PHY clock:
echo 4 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for all clock:
echo 7 > /sys/kernel/debug/<display_name>/config_clock_gating
To disable clock gating for all clocks:
echo 8 > /sys/kernel/debug/<display_name>/config_clock_gating
To go back to default setting:
echo 0 > /sys/kernel/debug/<display_name>/config_clock_gating
Change-Id: I83713d86eb1b9675d40d51fc20de81cca0aeb1c0
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Change updates dsi clock calculations for command mode
as per recommendation. Now dsi clocks are tied to
frame transer time. Propagate correct frame transfer
time to hal to update mdp clocks and bandwidth needed
accordingly.
Change-Id: I46f9038622ddd47cc53c5f3d54229f69a7008c8a
Signed-off-by: Vara Reddy <varar@codeaurora.org>
DSI display may support video mode and command mode both and it may
support transition between these two modes.
This change adds seamless transition between these two modes for DSI
display by avoiding crtc enable/disable and panel power on/off
during modeset.
Change-Id: Id7ddaef7d1f0f7cc7d52283755bad53a246adec6
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
