2 次程式碼提交

作者	SHA1	備註	日期
Santosh Kumar Aenugu	6add9d0fc0	disp: msm: dsi: fix dsi pll dividers ... Updating DSI PLL byte clock dividers as per HW recommendation. Change-Id: I9dbe7a04f813676a7690d0cadc52d7ed19ca4871 Signed-off-by: Santosh Kumar Aenugu <santoshkumar@codeaurora.org>	2021-05-25 08:13:55 -07:00
Satya Rama Aditya Pinapala	0a93edbae6	disp: msm: dsi: rework DSI PLL to be configured within PHY ... Change avoids clock framework APIs to configure the DSI PHY PLL. It follows HW recommendation to set the byte and pclk dividers. Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>	2021-01-12 23:49:11 -08:00