This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This change updates vreg_ctrl_0 and vreg_ctrl_1 settings for
cape DPHY as per the HW recommendation.
Change-Id: Ide66c62d980b57de1f826ed24d1c0747d8fb6c77
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Cape uses phy version 4.3 but requires programming of
different values for vreg_ctrl_0 and vreg_ctrl_1 to
configure LDO setting. Add new phy compatible string
to distinguish cape from other chipsets and program
the registers accordingly.
Change-Id: I68b266cc6e179d211ee0fd05584a605f39b4d31d
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Creating a generic api that can be used with the driver
for read poll timeouts. This allows for easy overriding
of the function, if necessary.
Change-Id: I7bc5176ebabe782089b1a4d6e94c17ad3eb9ada4
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Michael Ru <mru@codeaurora.org>
There is a new clock lane that is used for the sublink when
split link is enabled. The following change adds programming
to control the sublink clock lane.
Change-Id: I1af370cd39e02130569815766fb748ae6bad72d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The change updates DSI DPHY and CPHY programming for
PHY version 4_3.
Change-Id: Id6b5cfefdce9530891e1e0f5a34814606954d843
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change adds the new compatible version strings for DSI PHY and DSI CTRL
for waipio.
Change-Id: I1073034e608cace9d41cc04a9854f15f56828dfe
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds support for C-PHY dynamic clock switch feature.
Also add support for phy ver 4.0 C-PHY timing parameters calculation
to be used for clock switch.
Change-Id: I8292860fd8c93a7ba7988ec8c44ea9683f45b6e6
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change allows dynamic refresh trigger to sw trigger
and mdp intf flush. With this we can make sure that DSI
timing/clock update and mdp intf timings are updated in
one vsync.
Change-Id: Ic807f498e2e47be6dd0f1e11ff1fc0896a8ec758
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Change updates the DSI DPHY and CPHY settings as per
hardware recommendations.
Change-Id: I3472ab0214c2c915a3f68893dd4b19edd36bb26d
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add support to read cphy boolean flag from panel dtsi
and configure DSI PHY registers accordingly. Update the
bit/byte clock calculation according to cphy specifications.
Update clock parents so that the relevant divider blocks
are configured to support cphy.
Change-Id: Iaca61eec01a488657b086f59910c52f8c79e26a4
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
DSI PLL is tightly coupled with DSI PHY. This change removes
separate DSI pll driver and makes DSI pll as a subnode to DSI
PHY which is an accurate way of representation. In addition, this
change adds support for 5nm DSI ctrl and PHY revisions and adds
DSI pll support for 5nm. Remove support for older DSI pll revisions
such as 7nm, 10nm, 14nm, 20nm, 28nm.
Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
DSI PHY timings must be committed every time the values
are updated after a dynamic mode switch.
Change-Id: Id605c76dfe75ec41ceb89000f24baccda189e82f
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Adding debug, info and error prefix for log messages
in dsi files. To enable debug logs
run "echo 0x1 > /sys/module/drm/parameters/debug"
Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.
Change-Id: I20f6a81bb1112e9e976acae595b985dad7ad4b7a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change is a snapshot of dsi files taken of 4.14
as of commit 764f7c2 (Merge remote-tracking branch
'quic/dev/msm-4.14-display' into msm-4.14)
Change-Id: I8361a844c35a4450f7800964a8da2741676fd6c7
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.
Change-Id: I110cc5044d2676ade58f947b3efca53d1d72753c
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. DSI PHY V4 support is added.
Change-Id: I5bdbd6d2916692087c0192d23c8e7598238f161f
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
For some phy ver 4 chipsets, DSI_PHY_CMN_CTRL_4 needs to be programmed
in normal power up sequence. This change adds support to program the
same based on minor phy version.
Change-Id: I68bed48ca671f540efafd13f8d56c7e90de8b25c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
