qcacmn: HIF changes to support Moselle

Add HIF changes for supporting the newly
added IPCI bus type for Moselle

CRs-Fixed: 2597321
Change-Id: I9097e4622e9d6d561e92f5a21cb279c4d631cfbb

hif/inc/hif.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -64,6 +64,7 @@ typedef void *hif_handle_t;
 #define HIF_TYPE_QCA6018  20
 #define HIF_TYPE_QCN9000 21
 #define HIF_TYPE_QCA6490 22
+#define HIF_TYPE_QCA6750 23
 
 #ifdef IPA_OFFLOAD
 #define DMA_COHERENT_MASK_IPA_VER_3_AND_ABOVE   37

hif/inc/hostdef.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016,2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2016,2018-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -36,6 +36,8 @@ extern struct hostdef_s *QCA9888_HOSTdef;
 extern struct hostdef_s *QCA6290_HOSTdef;
 extern struct hostdef_s *QCA6390_HOSTdef;
 extern struct hostdef_s *QCA6490_HOSTdef;
+extern struct hostdef_s *QCA6750_HOSTdef;
+
 #ifdef ATH_AHB
 extern struct hostdef_s *IPQ4019_HOSTdef;
 #endif

hif/inc/regtable.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -32,4 +32,8 @@
 #include "regtable_usb.h"
 #endif
 
+#if defined(HIF_IPCI)
+#include "reg_struct.h"
+#include "regtable_ipcie.h"
+#endif
 #endif

hif/inc/regtable_ipcie.h

@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REGTABLE_IPCIE_H_
+#define _REGTABLE_IPCIE_H_
+
+#define MISSING  0
+
+#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
+	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
+#define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
+	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
+#define A_SOC_CORE_SPARE_1_REGISTER \
+	(scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
+#define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \
+	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
+#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \
+	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
+#define A_SOC_PCIE_PCIE_SCRATCH_0 \
+	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
+#define A_SOC_PCIE_PCIE_SCRATCH_1 \
+	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
+#define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \
+	(scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
+#define A_SOC_PCIE_PCIE_SCRATCH_2 \
+	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
+/* end Q6 iHelium emu registers */
+
+#define PCIE_INTR_FIRMWARE_ROUTE_MASK \
+	(scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
+#define A_SOC_CORE_SPARE_0_REGISTER \
+	(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
+#define A_SOC_CORE_SCRATCH_0_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
+#define A_SOC_CORE_SCRATCH_1_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
+#define A_SOC_CORE_SCRATCH_2_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
+#define A_SOC_CORE_SCRATCH_3_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
+#define A_SOC_CORE_SCRATCH_4_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
+#define A_SOC_CORE_SCRATCH_5_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
+#define A_SOC_CORE_SCRATCH_6_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
+#define A_SOC_CORE_SCRATCH_7_ADDRESS  \
+	(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
+#define RTC_SOC_BASE_ADDRESS  (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
+#define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
+#define SYSTEM_SLEEP_OFFSET   (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
+#define WLAN_SYSTEM_SLEEP_OFFSET \
+	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
+	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
+	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
+#define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
+#define CLOCK_CONTROL_SI0_CLK_MASK \
+	(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
+#define RESET_CONTROL_OFFSET    (scn->targetdef->d_RESET_CONTROL_OFFSET)
+#define RESET_CONTROL_MBOX_RST_MASK \
+	(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
+#define RESET_CONTROL_SI0_RST_MASK \
+	(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
+#define WLAN_RESET_CONTROL_OFFSET \
+	(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
+#define WLAN_RESET_CONTROL_COLD_RST_MASK \
+	(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
+#define WLAN_RESET_CONTROL_WARM_RST_MASK \
+	(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
+#define GPIO_BASE_ADDRESS       (scn->targetdef->d_GPIO_BASE_ADDRESS)
+#define GPIO_PIN0_OFFSET        (scn->targetdef->d_GPIO_PIN0_OFFSET)
+#define GPIO_PIN1_OFFSET        (scn->targetdef->d_GPIO_PIN1_OFFSET)
+#define GPIO_PIN0_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
+#define GPIO_PIN1_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
+#define A_SOC_CORE_SCRATCH_0    (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
+#define SI_CONFIG_BIDIR_OD_DATA_LSB \
+	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
+#define SI_CONFIG_BIDIR_OD_DATA_MASK \
+	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_LSB       (scn->targetdef->d_SI_CONFIG_I2C_LSB)
+#define SI_CONFIG_I2C_MASK \
+	(scn->targetdef->d_SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_LSB \
+	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
+#define SI_CONFIG_POS_SAMPLE_MASK \
+	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_LSB \
+	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
+#define SI_CONFIG_INACTIVE_CLK_MASK \
+	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_LSB \
+	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
+#define SI_CONFIG_INACTIVE_DATA_MASK \
+	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_LSB   (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
+#define SI_CONFIG_DIVIDER_MASK  (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
+#define SI_BASE_ADDRESS         (scn->targetdef->d_SI_BASE_ADDRESS)
+#define SI_CONFIG_OFFSET        (scn->targetdef->d_SI_CONFIG_OFFSET)
+#define SI_TX_DATA0_OFFSET      (scn->targetdef->d_SI_TX_DATA0_OFFSET)
+#define SI_TX_DATA1_OFFSET      (scn->targetdef->d_SI_TX_DATA1_OFFSET)
+#define SI_RX_DATA0_OFFSET      (scn->targetdef->d_SI_RX_DATA0_OFFSET)
+#define SI_RX_DATA1_OFFSET      (scn->targetdef->d_SI_RX_DATA1_OFFSET)
+#define SI_CS_OFFSET            (scn->targetdef->d_SI_CS_OFFSET)
+#define SI_CS_DONE_ERR_MASK     (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
+#define SI_CS_DONE_INT_MASK     (scn->targetdef->d_SI_CS_DONE_INT_MASK)
+#define SI_CS_START_LSB         (scn->targetdef->d_SI_CS_START_LSB)
+#define SI_CS_START_MASK        (scn->targetdef->d_SI_CS_START_MASK)
+#define SI_CS_RX_CNT_LSB        (scn->targetdef->d_SI_CS_RX_CNT_LSB)
+#define SI_CS_RX_CNT_MASK       (scn->targetdef->d_SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_LSB        (scn->targetdef->d_SI_CS_TX_CNT_LSB)
+#define SI_CS_TX_CNT_MASK       (scn->targetdef->d_SI_CS_TX_CNT_MASK)
+#define EEPROM_SZ               (scn->targetdef->d_BOARD_DATA_SZ)
+#define EEPROM_EXT_SZ           (scn->targetdef->d_BOARD_EXT_DATA_SZ)
+#define MBOX_BASE_ADDRESS       (scn->targetdef->d_MBOX_BASE_ADDRESS)
+#define LOCAL_SCRATCH_OFFSET    (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
+#define CPU_CLOCK_OFFSET        (scn->targetdef->d_CPU_CLOCK_OFFSET)
+#define LPO_CAL_OFFSET          (scn->targetdef->d_LPO_CAL_OFFSET)
+#define GPIO_PIN10_OFFSET       (scn->targetdef->d_GPIO_PIN10_OFFSET)
+#define GPIO_PIN11_OFFSET       (scn->targetdef->d_GPIO_PIN11_OFFSET)
+#define GPIO_PIN12_OFFSET       (scn->targetdef->d_GPIO_PIN12_OFFSET)
+#define GPIO_PIN13_OFFSET       (scn->targetdef->d_GPIO_PIN13_OFFSET)
+#define CLOCK_GPIO_OFFSET       (scn->targetdef->d_CLOCK_GPIO_OFFSET)
+#define CPU_CLOCK_STANDARD_LSB  (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
+#define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
+#define LPO_CAL_ENABLE_LSB      (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
+#define LPO_CAL_ENABLE_MASK     (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
+	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
+	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
+#define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
+#define WLAN_MAC_BASE_ADDRESS    (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
+#define FW_INDICATOR_ADDRESS     (scn->targetdef->d_FW_INDICATOR_ADDRESS)
+#define DRAM_BASE_ADDRESS        (scn->targetdef->d_DRAM_BASE_ADDRESS)
+#define SOC_CORE_BASE_ADDRESS    (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
+#define CORE_CTRL_ADDRESS        (scn->targetdef->d_CORE_CTRL_ADDRESS)
+#define CE_COUNT                 (scn->targetdef->d_CE_COUNT)
+#define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
+#define PCIE_INTR_CLR_ADDRESS    (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
+#define PCIE_INTR_FIRMWARE_MASK  (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
+#define PCIE_INTR_CE_MASK_ALL    (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
+#define CORE_CTRL_CPU_INTR_MASK  (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
+#define PCIE_INTR_CAUSE_ADDRESS  (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
+#define SOC_RESET_CONTROL_ADDRESS  (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
+#define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \
+	A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
+#define SOC_RESET_CONTROL_CE_RST_MASK \
+	(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
+#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
+	(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
+#define CPU_INTR_ADDRESS        (scn->targetdef->d_CPU_INTR_ADDRESS)
+#define SOC_LF_TIMER_CONTROL0_ADDRESS \
+	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
+#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
+	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define SOC_LF_TIMER_STATUS0_ADDRESS \
+	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
+	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
+	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
+
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
+	(((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
+	 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
+	(((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
+		SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
+
+/* hif_ipci.c */
+#define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
+#define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
+#define SOC_CHIP_ID_REVISION_LSB  (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
+#define SOC_CHIP_ID_VERSION_MASK  (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
+#define SOC_CHIP_ID_VERSION_LSB   (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
+#define CHIP_ID_REVISION_GET(x) \
+	(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
+#define CHIP_ID_VERSION_GET(x) \
+	(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
+/* hif_ipci.c end */
+
+/* misc */
+#define SR_WR_INDEX_ADDRESS     (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
+#define DST_WATERMARK_ADDRESS   (scn->targetdef->d_DST_WATERMARK_ADDRESS)
+#define SOC_POWER_REG_OFFSET    (scn->targetdef->d_SOC_POWER_REG_OFFSET)
+/* end */
+
+/* copy_engine.c */
+/* end */
+/* PLL start */
+#define EFUSE_OFFSET              (scn->targetdef->d_EFUSE_OFFSET)
+#define EFUSE_XTAL_SEL_MSB        (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
+#define EFUSE_XTAL_SEL_LSB        (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
+#define EFUSE_XTAL_SEL_MASK       (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
+#define BB_PLL_CONFIG_OFFSET      (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
+#define BB_PLL_CONFIG_OUTDIV_MSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
+#define BB_PLL_CONFIG_OUTDIV_LSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
+#define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
+#define BB_PLL_CONFIG_FRAC_MSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
+#define BB_PLL_CONFIG_FRAC_LSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
+#define BB_PLL_CONFIG_FRAC_MASK   (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
+#define WLAN_PLL_SETTLE_TIME_MSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
+#define WLAN_PLL_SETTLE_TIME_LSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
+#define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
+#define WLAN_PLL_SETTLE_OFFSET    (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
+#define WLAN_PLL_SETTLE_SW_MASK   (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
+#define WLAN_PLL_SETTLE_RSTMASK   (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
+#define WLAN_PLL_SETTLE_RESET     (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
+#define WLAN_PLL_CONTROL_NOPWD_MSB  \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
+#define WLAN_PLL_CONTROL_NOPWD_LSB  \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
+#define WLAN_PLL_CONTROL_NOPWD_MASK \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_MSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
+#define WLAN_PLL_CONTROL_BYPASS_LSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
+#define WLAN_PLL_CONTROL_BYPASS_MASK \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_RESET \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
+#define WLAN_PLL_CONTROL_CLK_SEL_MSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
+#define WLAN_PLL_CONTROL_CLK_SEL_LSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
+#define WLAN_PLL_CONTROL_CLK_SEL_MASK \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
+#define WLAN_PLL_CONTROL_CLK_SEL_RESET \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
+#define WLAN_PLL_CONTROL_REFDIV_MSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
+#define WLAN_PLL_CONTROL_REFDIV_LSB \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
+#define WLAN_PLL_CONTROL_REFDIV_MASK \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
+#define WLAN_PLL_CONTROL_REFDIV_RESET \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
+#define WLAN_PLL_CONTROL_DIV_MSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
+#define WLAN_PLL_CONTROL_DIV_LSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
+#define WLAN_PLL_CONTROL_DIV_MASK  (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
+#define WLAN_PLL_CONTROL_DIV_RESET \
+	(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
+#define WLAN_PLL_CONTROL_OFFSET    (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
+#define WLAN_PLL_CONTROL_SW_MASK   (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
+#define WLAN_PLL_CONTROL_RSTMASK   (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
+#define WLAN_PLL_CONTROL_RESET     (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
+#define SOC_CORE_CLK_CTRL_OFFSET   (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
+#define SOC_CORE_CLK_CTRL_DIV_MSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
+#define SOC_CORE_CLK_CTRL_DIV_LSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
+#define SOC_CORE_CLK_CTRL_DIV_MASK \
+	(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
+#define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
+	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
+#define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
+	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
+#define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
+	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
+#define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
+	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
+#define RTC_SYNC_STATUS_OFFSET      (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
+#define SOC_CPU_CLOCK_OFFSET        (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
+#define SOC_CPU_CLOCK_STANDARD_MSB \
+	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
+#define SOC_CPU_CLOCK_STANDARD_LSB \
+	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
+#define SOC_CPU_CLOCK_STANDARD_MASK \
+	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
+/* PLL end */
+
+#define FW_CPU_PLL_CONFIG \
+	(scn->targetdef->d_FW_CPU_PLL_CONFIG)
+
+#define WIFICMN_PCIE_BAR_REG_ADDRESS \
+	(sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS)
+
+    /* htt tx */
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK)
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK)
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK)
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK)
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB)
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB)
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB)
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  \
+	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB)
+
+#define CE_CMD_ADDRESS            \
+	(scn->targetdef->d_CE_CMD_ADDRESS)
+#define CE_CMD_HALT_MASK          \
+	(scn->targetdef->d_CE_CMD_HALT_MASK)
+#define CE_CMD_HALT_STATUS_MASK   \
+	(scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
+#define CE_CMD_HALT_STATUS_LSB    \
+	(scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
+
+#define SI_CONFIG_ERR_INT_MASK       \
+	(scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
+#define SI_CONFIG_ERR_INT_LSB        \
+	(scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
+#define GPIO_ENABLE_W1TS_LOW_ADDRESS \
+	(scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
+#define GPIO_PIN0_CONFIG_LSB         \
+	(scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
+#define GPIO_PIN0_PAD_PULL_LSB       \
+	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
+#define GPIO_PIN0_PAD_PULL_MASK      \
+	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
+
+#define SOC_CHIP_ID_REVISION_MSB \
+	(scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
+
+#define FW_AXI_MSI_ADDR                \
+	(scn->targetdef->d_FW_AXI_MSI_ADDR)
+#define FW_AXI_MSI_DATA                \
+	(scn->targetdef->d_FW_AXI_MSI_DATA)
+#define WLAN_SUBSYSTEM_CORE_ID_ADDRESS \
+	(scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
+#define FPGA_VERSION_ADDRESS           \
+	(scn->targetdef->d_FPGA_VERSION_ADDRESS)
+
+/* SET macros */
+#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
+	(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
+	    WLAN_SYSTEM_SLEEP_DISABLE_MASK)
+#define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
+	(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
+#define SI_CONFIG_I2C_SET(x)  (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
+#define SI_CONFIG_POS_SAMPLE_SET(x) \
+	(((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
+#define SI_CONFIG_INACTIVE_CLK_SET(x) \
+	(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
+#define SI_CONFIG_INACTIVE_DATA_SET(x) \
+	(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
+#define SI_CONFIG_DIVIDER_SET(x) \
+	(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
+#define SI_CS_START_SET(x)  (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
+#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
+#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
+#define LPO_CAL_ENABLE_SET(x) \
+	(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
+#define CPU_CLOCK_STANDARD_SET(x) \
+	(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
+#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
+	(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
+/* copy_engine.c */
+/* end */
+/* PLL start */
+#define EFUSE_XTAL_SEL_GET(x) \
+	(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
+#define EFUSE_XTAL_SEL_SET(x) \
+	(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
+#define BB_PLL_CONFIG_OUTDIV_GET(x) \
+	(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
+#define BB_PLL_CONFIG_OUTDIV_SET(x) \
+	(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
+#define BB_PLL_CONFIG_FRAC_GET(x) \
+	(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
+#define BB_PLL_CONFIG_FRAC_SET(x) \
+	(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
+#define WLAN_PLL_SETTLE_TIME_GET(x) \
+	(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
+#define WLAN_PLL_SETTLE_TIME_SET(x) \
+	(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
+#define WLAN_PLL_CONTROL_NOPWD_GET(x) \
+	(((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
+#define WLAN_PLL_CONTROL_NOPWD_SET(x) \
+	(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
+#define WLAN_PLL_CONTROL_BYPASS_GET(x) \
+	(((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
+#define WLAN_PLL_CONTROL_BYPASS_SET(x) \
+	(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
+#define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
+	(((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
+#define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
+	(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
+#define WLAN_PLL_CONTROL_REFDIV_GET(x) \
+	(((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
+#define WLAN_PLL_CONTROL_REFDIV_SET(x) \
+	(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
+#define WLAN_PLL_CONTROL_DIV_GET(x) \
+	(((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
+#define WLAN_PLL_CONTROL_DIV_SET(x) \
+	(((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
+#define SOC_CORE_CLK_CTRL_DIV_GET(x) \
+	(((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
+#define SOC_CORE_CLK_CTRL_DIV_SET(x) \
+	(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
+#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
+	(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
+		RTC_SYNC_STATUS_PLL_CHANGING_LSB)
+#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
+	(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
+		RTC_SYNC_STATUS_PLL_CHANGING_MASK)
+#define SOC_CPU_CLOCK_STANDARD_GET(x) \
+	(((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
+#define SOC_CPU_CLOCK_STANDARD_SET(x) \
+	(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
+/* PLL end */
+#define WLAN_GPIO_PIN0_CONFIG_SET(x)   \
+	(((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
+#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) \
+	(((x) << GPIO_PIN0_PAD_PULL_LSB) & GPIO_PIN0_PAD_PULL_MASK)
+#define SI_CONFIG_ERR_INT_SET(x)       \
+	(((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
+
+#ifdef QCA_WIFI_3_0_ADRASTEA
+#define Q6_ENABLE_REGISTER_0 \
+	(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
+#define Q6_ENABLE_REGISTER_1 \
+	(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
+#define Q6_CAUSE_REGISTER_0 \
+	(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
+#define Q6_CAUSE_REGISTER_1 \
+	(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
+#define Q6_CLEAR_REGISTER_0 \
+	(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
+#define Q6_CLEAR_REGISTER_1 \
+	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
+#endif
+
+#ifdef CONFIG_BYPASS_QMI
+#define BYPASS_QMI_TEMP_REGISTER \
+	(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)
+#endif
+
+#define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
+#define DESC_DATA_FLAG_MASK        (scn->hostdef->d_DESC_DATA_FLAG_MASK)
+#define MUX_ID_MASK                (scn->hostdef->d_MUX_ID_MASK)
+#define TRANSACTION_ID_MASK        (scn->hostdef->d_TRANSACTION_ID_MASK)
+#define HOST_CE_COUNT              (scn->hostdef->d_HOST_CE_COUNT)
+#define ENABLE_MSI                 (scn->hostdef->d_ENABLE_MSI)
+#define INT_STATUS_ENABLE_ERROR_LSB \
+	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_MASK \
+	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_LSB  (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_COUNTER_LSB \
+	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_MASK \
+	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB \
+	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK \
+	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
+	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
+	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
+	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
+	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
+	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
+	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+#define INT_STATUS_ENABLE_ADDRESS \
+	(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
+#define CPU_INT_STATUS_ENABLE_BIT_LSB \
+	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_MASK \
+	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
+#define HOST_INT_STATUS_ADDRESS     (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
+#define CPU_INT_STATUS_ADDRESS      (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
+#define ERROR_INT_STATUS_ADDRESS    (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
+#define ERROR_INT_STATUS_WAKEUP_MASK \
+	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
+#define ERROR_INT_STATUS_WAKEUP_LSB \
+	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
+	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
+	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
+	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
+	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define COUNT_DEC_ADDRESS          (scn->hostdef->d_COUNT_DEC_ADDRESS)
+#define HOST_INT_STATUS_CPU_MASK   (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
+#define HOST_INT_STATUS_CPU_LSB    (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
+#define HOST_INT_STATUS_ERROR_LSB  (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_COUNTER_MASK \
+	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
+#define HOST_INT_STATUS_COUNTER_LSB \
+	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
+#define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
+#define WINDOW_DATA_ADDRESS        (scn->hostdef->d_WINDOW_DATA_ADDRESS)
+#define WINDOW_READ_ADDR_ADDRESS   (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
+#define WINDOW_WRITE_ADDR_ADDRESS  (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
+#define SOC_GLOBAL_RESET_ADDRESS   (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
+#define RTC_STATE_ADDRESS          (scn->hostdef->d_RTC_STATE_ADDRESS)
+#define RTC_STATE_COLD_RESET_MASK  (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
+#define PCIE_LOCAL_BASE_ADDRESS    (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
+#define PCIE_SOC_WAKE_RESET        (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
+#define PCIE_SOC_WAKE_ADDRESS      (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
+#define PCIE_SOC_WAKE_V_MASK       (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
+#define RTC_STATE_V_MASK           (scn->hostdef->d_RTC_STATE_V_MASK)
+#define RTC_STATE_V_LSB            (scn->hostdef->d_RTC_STATE_V_LSB)
+#define FW_IND_EVENT_PENDING       (scn->hostdef->d_FW_IND_EVENT_PENDING)
+#define FW_IND_INITIALIZED         (scn->hostdef->d_FW_IND_INITIALIZED)
+#define FW_IND_HELPER              (scn->hostdef->d_FW_IND_HELPER)
+#define RTC_STATE_V_ON             (scn->hostdef->d_RTC_STATE_V_ON)
+
+#define FW_IND_HOST_READY          (scn->hostdef->d_FW_IND_HOST_READY)
+
+#if defined(SDIO_3_0)
+#define HOST_INT_STATUS_MBOX_DATA_MASK \
+	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
+#define HOST_INT_STATUS_MBOX_DATA_LSB \
+	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
+#endif
+
+#if !defined(SOC_PCIE_BASE_ADDRESS)
+#define SOC_PCIE_BASE_ADDRESS 0
+#endif
+
+#if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
+#define PCIE_SOC_RDY_STATUS_ADDRESS 0
+#define PCIE_SOC_RDY_STATUS_BAR_MASK 0
+#endif
+
+#if !defined(MSI_MAGIC_ADR_ADDRESS)
+#define MSI_MAGIC_ADR_ADDRESS 0
+#define MSI_MAGIC_ADDRESS 0
+#endif
+
+/* SET/GET macros */
+#define INT_STATUS_ENABLE_ERROR_SET(x) \
+	(((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+#define INT_STATUS_ENABLE_CPU_SET(x) \
+	(((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+#define INT_STATUS_ENABLE_COUNTER_SET(x) \
+	(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
+		INT_STATUS_ENABLE_COUNTER_MASK)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
+	(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
+	 INT_STATUS_ENABLE_MBOX_DATA_MASK)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
+	(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
+		CPU_INT_STATUS_ENABLE_BIT_MASK)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
+	(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
+		ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
+	(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
+		ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
+	(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
+		COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+#define ERROR_INT_STATUS_WAKEUP_GET(x) \
+	(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
+		ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
+	(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
+		ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
+	(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
+		ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define HOST_INT_STATUS_CPU_GET(x) \
+	(((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_ERROR_GET(x) \
+	(((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_COUNTER_GET(x) \
+	(((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define RTC_STATE_V_GET(x) \
+	(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
+#if defined(SDIO_3_0)
+#define HOST_INT_STATUS_MBOX_DATA_GET(x) \
+	(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
+		HOST_INT_STATUS_MBOX_DATA_LSB)
+#endif
+
+#define INVALID_REG_LOC_DUMMY_DATA 0xAA
+
+#define AR6320_CORE_CLK_DIV_ADDR        0x403fa8
+#define AR6320_CPU_PLL_INIT_DONE_ADDR   0x403fd0
+#define AR6320_CPU_SPEED_ADDR           0x403fa4
+#define AR6320V2_CORE_CLK_DIV_ADDR      0x403fd8
+#define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
+#define AR6320V2_CPU_SPEED_ADDR         0x403fd4
+#define AR6320V3_CORE_CLK_DIV_ADDR      0x404028
+#define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
+#define AR6320V3_CPU_SPEED_ADDR         0x404024
+
+enum a_refclk_speed_t {
+	SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
+	SOC_REFCLK_48_MHZ = 0,
+	SOC_REFCLK_19_2_MHZ = 1,
+	SOC_REFCLK_24_MHZ = 2,
+	SOC_REFCLK_26_MHZ = 3,
+	SOC_REFCLK_37_4_MHZ = 4,
+	SOC_REFCLK_38_4_MHZ = 5,
+	SOC_REFCLK_40_MHZ = 6,
+	SOC_REFCLK_52_MHZ = 7,
+};
+
+#define A_REFCLK_UNKNOWN    SOC_REFCLK_UNKNOWN
+#define A_REFCLK_48_MHZ     SOC_REFCLK_48_MHZ
+#define A_REFCLK_19_2_MHZ   SOC_REFCLK_19_2_MHZ
+#define A_REFCLK_24_MHZ     SOC_REFCLK_24_MHZ
+#define A_REFCLK_26_MHZ     SOC_REFCLK_26_MHZ
+#define A_REFCLK_37_4_MHZ   SOC_REFCLK_37_4_MHZ
+#define A_REFCLK_38_4_MHZ   SOC_REFCLK_38_4_MHZ
+#define A_REFCLK_40_MHZ     SOC_REFCLK_40_MHZ
+#define A_REFCLK_52_MHZ     SOC_REFCLK_52_MHZ
+
+#define TARGET_CPU_FREQ 176000000
+
+struct wlan_pll_s {
+	uint32_t refdiv;
+	uint32_t div;
+	uint32_t rnfrac;
+	uint32_t outdiv;
+};
+
+struct cmnos_clock_s {
+	enum a_refclk_speed_t refclk_speed;
+	uint32_t refclk_hz;
+	uint32_t pll_settling_time;     /* 50us */
+	struct wlan_pll_s wlan_pll;
+};
+
+struct tgt_reg_section {
+	uint32_t start_addr;
+	uint32_t end_addr;
+};
+
+struct tgt_reg_table {
+	const struct tgt_reg_section *section;
+	uint32_t section_size;
+};
+
+struct hif_softc;
+void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
+void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);
+
+#endif /* _REGTABLE_IPCIE_H_ */

hif/inc/target_type.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -59,6 +59,11 @@ extern "C" {
 #define TARGET_TYPE_QCA6490   27
 #endif
 
+/* Moselle */
+#ifndef TARGET_TYPE_QCA6750
+#define TARGET_TYPE_QCA6750 28
+#endif
+
 #ifdef __cplusplus
 }
 #endif

hif/inc/targetdef.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016,2018-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2016,2018-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -36,6 +36,8 @@ extern struct targetdef_s *QCA9888_TARGETdef;
 extern struct targetdef_s *QCA6290_TARGETdef;
 extern struct targetdef_s *QCA6390_TARGETdef;
 extern struct targetdef_s *QCA6490_TARGETdef;
+extern struct targetdef_s *QCA6750_TARGETdef;
+
 #ifdef ATH_AHB
 extern struct targetdef_s *IPQ4019_TARGETdef;
 #endif
@@ -56,6 +58,7 @@ extern struct ce_reg_def *QCA9888_CE_TARGETdef;
 extern struct ce_reg_def *QCA6290_CE_TARGETdef;
 extern struct ce_reg_def *QCA6390_CE_TARGETdef;
 extern struct ce_reg_def *QCA6490_CE_TARGETdef;
+extern struct ce_reg_def *QCA6750_CE_TARGETdef;
 #ifdef ATH_AHB
 extern struct ce_reg_def *IPQ4019_CE_TARGETdef;
 #endif

hif/src/ar6320def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -97,7 +97,8 @@
 #define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
 #define AR6320_RX_MPDU_START_2_TID_LSB                  28
 #define AR6320_RX_MPDU_START_2_TID_MASK                 0xf0000000
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 #define AR6320_SOC_PCIE_BASE_ADDRESS                    0x00038000
 #define AR6320_CE_WRAPPER_BASE_ADDRESS                  0x00034000
 #define AR6320_CE0_BASE_ADDRESS                         0x00034400
@@ -218,7 +219,8 @@
 #define AR6320_SOC_CHIP_ID_VERSION_LSB                  18
 #define AR6320_SOC_CHIP_ID_REVISION_MASK                0x00000f00
 #define AR6320_SOC_CHIP_ID_REVISION_LSB                 8
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 #define AR6320_SOC_POWER_REG_OFFSET                     0x0000010c
 /* Copy Engine Debug */
 #define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
@@ -452,7 +454,8 @@ struct targetdef_s ar6320_targetdef = {
 	.d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS,
 	.d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS,
 	.d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS,
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
 #endif
@@ -513,7 +516,8 @@ struct targetdef_s ar6320_targetdef = {
 		AR6320_RX_ATTENTION_0_MSDU_DONE_MASK,
 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
 		AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 	.d_CE_COUNT = AR6320_CE_COUNT,
 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
 	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
@@ -696,7 +700,8 @@ struct hostdef_s ar6320_hostdef = {
 	.d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS,
 	.d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS,
 	.d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK,
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 	.d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS,
 	.d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET,
 	.d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS,
@@ -725,7 +730,8 @@ struct hostdef_s ar6320_hostdef = {
 #endif
 };
 
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 struct ce_reg_def ar6320_ce_targetdef = {
 	/* copy_engine.c  */
 	.d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS,

hif/src/ar6320v2def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -182,7 +182,8 @@
 #if defined(HIF_SDIO)
 #define AR6320V2_FW_IND_HELPER                            4
 #endif
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 #define AR6320V2_CE_WRAPPER_BASE_ADDRESS                  0x00034000
 #define AR6320V2_CE0_BASE_ADDRESS                         0x00034400
 #define AR6320V2_CE1_BASE_ADDRESS                         0x00034800
@@ -459,7 +460,8 @@ struct targetdef_s ar6320v2_targetdef = {
 	.d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS,
 	.d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS,
 	.d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS,
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
 	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
 #endif
@@ -526,7 +528,8 @@ struct targetdef_s ar6320v2_targetdef = {
 		AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK,
 	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
 		AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 	.d_CE_COUNT = AR6320V2_CE_COUNT,
 	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
 	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
@@ -728,7 +731,8 @@ struct hostdef_s ar6320v2_hostdef = {
 	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
 		AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB,
 #endif
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 	.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
 	.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
 	.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
@@ -749,7 +753,8 @@ struct hostdef_s ar6320v2_hostdef = {
 #endif
 };
 
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 struct ce_reg_def ar6320v2_ce_targetdef = {
 	/* copy_engine.c  */
 	.d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS,

hif/src/ath_procfs.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, 2016-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2014, 2016-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -87,7 +87,9 @@ static ssize_t ath_procfs_diag_read(struct file *file, char __user *buf,
 	     (tgt_info->target_type == TARGET_TYPE_QCA8074) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCN9000) ||
-	     (tgt_info->target_type == TARGET_TYPE_QCA6018)))) {
+	     (tgt_info->target_type == TARGET_TYPE_QCA6018))) ||
+	    (scn->bus_type ==  QDF_BUS_TYPE_IPCI &&
+	     (tgt_info->target_type == TARGET_TYPE_QCA6750))) {
 		memtype = ((uint32_t)(*pos) & 0xff000000) >> 24;
 		offset = (uint32_t)(*pos) & 0xffffff;
 		HIF_DBG("%s: offset 0x%x memtype 0x%x, datalen %zu\n",
@@ -164,7 +166,9 @@ static ssize_t ath_procfs_diag_write(struct file *file,
 	      (tgt_info->target_type == TARGET_TYPE_QCA8074) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCN9000) ||
-	      (tgt_info->target_type == TARGET_TYPE_QCA6018)))) {
+	      (tgt_info->target_type == TARGET_TYPE_QCA6018))) ||
+	    (scn->bus_type ==  QDF_BUS_TYPE_IPCI &&
+	     (tgt_info->target_type == TARGET_TYPE_QCA6750))) {
 		memtype = ((uint32_t)(*pos) & 0xff000000) >> 24;
 		offset = (uint32_t)(*pos) & 0xffffff;
 		HIF_DBG("%s: offset 0x%x memtype 0x%x, datalen %zu\n",

hif/src/ce/ce_assignment.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -1169,4 +1169,53 @@ static struct CE_pipe_config target_ce_config_wlan_qca6490[] = {
 	{ /* CE8 */ 8, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
 	/* CE 9, 10, 11 belong to CoreBsp & MHI driver */
 };
+
+#define QCA_6750_CE_COUNT 9
+static struct CE_attr host_ce_config_wlan_qca6750[] = {
+	/* host->target HTC control and raw streams */
+	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
+	/* target->host HTT + HTC control */
+	{ /* CE1 */ CE_ATTR_FLAGS, 0, 0,  2048, 512, NULL,},
+	/* target->host WMI */
+	{ /* CE2 */ CE_ATTR_FLAGS, 0, 0,  2048, 32, NULL,},
+	/* host->target WMI */
+	{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
+	/* host->target HTT */
+	{ /* CE4 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
+		CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
+	/* target -> host PKTLOG */
+	{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 512, NULL,},
+	/* Target autonomous HIF_memcpy */
+	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
+	/* ce_diag, the Diagnostic Window */
+	{ /* CE7 */ (CE_ATTR_DIAG_FLAGS | CE_ATTR_DISABLE_INTR), 0,
+		0, DIAG_TRANSFER_LIMIT, 0, NULL,},
+	/* Reserved for target */
+	{ /* CE8 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
+	/* CE 9, 10, 11 belong to CoreBsp & MHI driver */
+};
+
+static struct CE_pipe_config target_ce_config_wlan_qca6750[] = {
+	/* host->target HTC control and raw streams */
+	{ /* CE0 */ 0, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
+	/* target->host HTT */
+	{ /* CE1 */ 1, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* target->host WMI  + HTC control */
+	{ /* CE2 */ 2, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* host->target WMI */
+	{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
+	/* host->target HTT */
+	{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256,
+		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
+	/* Target -> host PKTLOG */
+	{ /* CE5 */ 5, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* Reserved for target autonomous HIF_memcpy */
+	{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
+	/* CE7 used only by Host */
+	{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0,
+		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
+	/* Reserved for target */
+	{ /* CE8 */ 8, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
+	/* CE 9, 10, 11 belong to CoreBsp & MHI driver */
+};
 #endif /* __HIF_PCI_INTERNAL_H__ */

hif/src/ce/ce_main.c

@@ -631,6 +631,31 @@ static struct service_to_pipe target_service_to_ce_map_qca6490[] = {
 	{ 0, 0, 0, },
 };
 
+#if (defined(QCA_WIFI_QCA6750))
+static struct service_to_pipe target_service_to_ce_map_qca6750[] = {
+	{ WMI_DATA_VO_SVC, PIPEDIR_OUT, 3, },
+	{ WMI_DATA_VO_SVC, PIPEDIR_IN, 2, },
+	{ WMI_DATA_BK_SVC, PIPEDIR_OUT, 3, },
+	{ WMI_DATA_BK_SVC, PIPEDIR_IN, 2, },
+	{ WMI_DATA_BE_SVC, PIPEDIR_OUT, 3, },
+	{ WMI_DATA_BE_SVC, PIPEDIR_IN, 2, },
+	{ WMI_DATA_VI_SVC, PIPEDIR_OUT, 3, },
+	{ WMI_DATA_VI_SVC, PIPEDIR_IN, 2, },
+	{ WMI_CONTROL_SVC, PIPEDIR_OUT, 3, },
+	{ WMI_CONTROL_SVC, PIPEDIR_IN, 2, },
+	{ HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0, },
+	{ HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2, },
+	{ HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4, },
+	{ HTT_DATA_MSG_SVC, PIPEDIR_IN, 1, },
+	{ PACKET_LOG_SVC, PIPEDIR_IN, 5, },
+	/* (Additions here) */
+	{ 0, 0, 0, },
+};
+#else
+static struct service_to_pipe target_service_to_ce_map_qca6750[] = {
+};
+#endif
+
 static struct service_to_pipe target_service_to_ce_map_ar900b[] = {
 	{
 		WMI_DATA_VO_SVC,
@@ -827,6 +852,11 @@ static void hif_select_service_to_pipe_map(struct hif_softc *scn,
 			*sz_tgt_svc_map_to_use =
 				sizeof(target_service_to_ce_map_qca6490);
 			break;
+		case TARGET_TYPE_QCA6750:
+			*tgt_svc_map_to_use = target_service_to_ce_map_qca6750;
+			*sz_tgt_svc_map_to_use =
+				sizeof(target_service_to_ce_map_qca6750);
+			break;
 		case TARGET_TYPE_QCA8074:
 			*tgt_svc_map_to_use = target_service_to_ce_map_qca8074;
 			*sz_tgt_svc_map_to_use =
@@ -1058,6 +1088,7 @@ bool ce_srng_based(struct hif_softc *scn)
 	case TARGET_TYPE_QCA6290:
 	case TARGET_TYPE_QCA6390:
 	case TARGET_TYPE_QCA6490:
+	case TARGET_TYPE_QCA6750:
 	case TARGET_TYPE_QCA6018:
 	case TARGET_TYPE_QCN9000:
 		return true;
@@ -3212,6 +3243,14 @@ void hif_ce_prepare_config(struct hif_softc *scn)
 
 		scn->ce_count = QCA_6490_CE_COUNT;
 		break;
+	case TARGET_TYPE_QCA6750:
+		hif_state->host_ce_config = host_ce_config_wlan_qca6750;
+		hif_state->target_ce_config = target_ce_config_wlan_qca6750;
+		hif_state->target_ce_config_sz =
+					sizeof(target_ce_config_wlan_qca6750);
+
+		scn->ce_count = QCA_6750_CE_COUNT;
+		break;
 	case TARGET_TYPE_ADRASTEA:
 		if (hif_is_attribute_set(scn, HIF_LOWDESC_CE_NO_PKTLOG_CFG)) {
 			hif_state->host_ce_config =

hif/src/dispatcher/ipci_api.h

@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _IPCI_API_H_
+#define _IPCI_API_H_
+struct hif_exec_context;
+
+/**
+ * hif_ipci_open(): hif_bus_open
+ * @hif_ctx: hif context
+ * @bus_type: bus type
+ *
+ * Return: 0 for success or QDF_STATUS_E_NOMEM
+ */
+QDF_STATUS hif_ipci_open(struct hif_softc *hif_ctx,
+			 enum qdf_bus_type bus_type);
+
+/**
+ * hif_ipci_close(): hif_bus_close
+ * @hif_ctx: hif context
+ *
+ * Return: n/a
+ */
+void hif_ipci_close(struct hif_softc *hif_ctx);
+
+/**
+ * hif_bus_prevent_linkdown(): allow or permit linkdown
+ * @scn: struct hif_softc
+ * @flag: true prevents linkdown, false allows
+ *
+ * Calls into the platform driver to vote against taking down the
+ * pcie link.
+ *
+ * Return: n/a
+ */
+void hif_ipci_prevent_linkdown(struct hif_softc *scn, bool flag);
+
+/**
+ * hif_ipci_bus_suspend(): prepare hif for suspend
+ * @scn: struct hif_softc
+ *
+ * Return: Errno
+ */
+int hif_ipci_bus_suspend(struct hif_softc *scn);
+
+/**
+ * hif_ipci_bus_suspend_noirq() - ensure there are no pending transactions
+ * @scn: hif context
+ *
+ * Ensure that if we received the wakeup message before the irq
+ * was disabled that the message is pocessed before suspending.
+ *
+ * Return: -EBUSY if we fail to flush the tasklets.
+ */
+int hif_ipci_bus_suspend_noirq(struct hif_softc *scn);
+
+/**
+ * hif_ipci_bus_resume(): prepare hif for resume
+ * @scn: struct hif_softc
+ *
+ * Return: Errno
+ */
+int hif_ipci_bus_resume(struct hif_softc *scn);
+
+/**
+ * hif_ipci_bus_resume_noirq() - ensure there are no pending transactions
+ * @scn: hif context
+ *
+ * Ensure that if we received the wakeup message before the irq
+ * was disabled that the message is pocessed before suspending.
+ *
+ * Return: -EBUSY if we fail to flush the tasklets.
+ */
+int hif_ipci_bus_resume_noirq(struct hif_softc *scn);
+
+/**
+ * hif_ipci_disable_isr(): disable interrupt
+ * @scn: struct hif_softc
+ *
+ * Return: n/a
+ */
+void hif_ipci_disable_isr(struct hif_softc *scn);
+
+/**
+ * hif_ipci_nointrs(): disable IRQ
+ * @scn: struct hif_softc
+ *
+ * This function stops interrupt(s)
+ *
+ * Return: none
+ */
+void hif_ipci_nointrs(struct hif_softc *scn);
+
+/**
+ * hif_ipci_dump_registers(): dump bus debug registers
+ * @scn: struct hif_opaque_softc
+ *
+ * This function dumps hif bus debug registers
+ *
+ * Return: 0 for success or error code
+ */
+int hif_ipci_dump_registers(struct hif_softc *scn);
+
+/**
+ * hif_ipci_enable_bus(): enable bus
+ *
+ * This function enables the bus
+ *
+ * @ol_sc: soft_sc struct
+ * @dev: device pointer
+ * @bdev: bus dev pointer
+ * bid: bus id pointer
+ * type: enum hif_enable_type such as HIF_ENABLE_TYPE_PROBE
+ * Return: QDF_STATUS
+ */
+QDF_STATUS hif_ipci_enable_bus(
+			struct hif_softc *scn,
+			struct device *dev, void *bdev,
+			const struct hif_bus_id *bid,
+			enum hif_enable_type type);
+
+/**
+ * hif_ipci_disable_bus(): hif_disable_bus
+ *
+ * This function disables the bus
+ *
+ * @scn: struct hif_softc
+ *
+ * Return: none
+ */
+void hif_ipci_disable_bus(struct hif_softc *scn);
+
+/**
+ * hif_ipci_bus_configure() - configure the pcie bus
+ * @hif_sc: pointer to the hif context.
+ *
+ * return: 0 for success. nonzero for failure.
+ */
+int hif_ipci_bus_configure(struct hif_softc *scn);
+
+/**
+ * hif_ipci_enable_power_management() - enable power management
+ * @hif_ctx: hif context
+ * @is_packet_log_enabled: pktlog enabled or disabled
+ *
+ * Return: none
+ */
+void hif_ipci_enable_power_management(
+				struct hif_softc *hif_ctx,
+				bool is_packet_log_enabled);
+
+/**
+ * hif_ipci_disable_power_management() - disable power management
+ * @hif_ctx: hif context
+ *
+ * Return: none
+ */
+void hif_ipci_disable_power_management(struct hif_softc *hif_ctx);
+
+/**
+ * hif_ipci_configure_grp_irq() - configure HW block irq
+ * @scn: hif context
+ * @exec: hif exec context
+ *
+ * Return:Errno
+ */
+int hif_ipci_configure_grp_irq(
+			struct hif_softc *scn,
+			struct hif_exec_context *exec);
+
+/**
+ * hif_ipci_display_stats() - display stats
+ * @hif_ctx: hif context
+ *
+ * Return: none
+ */
+void hif_ipci_display_stats(struct hif_softc *hif_ctx);
+
+/**
+ * hif_ipci_clear_stats() - clear stats
+ * @hif_ctx: hif context
+ *
+ * Return: none
+ */
+void hif_ipci_clear_stats(struct hif_softc *hif_ctx);
+
+/**
+ * hif_ipci_needs_bmi() - return true if the soc needs bmi through the driver
+ * @scn: hif context
+ *
+ * Return: true if soc needs driver bmi otherwise false
+ */
+bool hif_ipci_needs_bmi(struct hif_softc *scn);
+
+/**
+ * hif_ipci_get_irq_name() - get irqname
+ * This function gives irqnumber to irqname
+ * mapping.
+ *
+ * @irq_no: irq number
+ *
+ * Return: irq name
+ */
+const char *hif_ipci_get_irq_name(int irq_no);
+
+#endif /* _IPCI_API_H_ */

hif/src/dispatcher/multibus.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -23,7 +23,8 @@
 #include "hif_io32.h"
 #include "multibus.h"
 #include "dummy.h"
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 #include "ce_main.h"
 #include "ce_api.h"
 #include "ce_internal.h"
@@ -96,6 +97,8 @@ int hif_bus_get_context_size(enum qdf_bus_type bus_type)
 	switch (bus_type) {
 	case QDF_BUS_TYPE_PCI:
 		return hif_pci_get_context_size();
+	case QDF_BUS_TYPE_IPCI:
+		return hif_ipci_get_context_size();
 	case QDF_BUS_TYPE_AHB:
 		return hif_ahb_get_context_size();
 	case QDF_BUS_TYPE_SNOC:
@@ -127,6 +130,9 @@ QDF_STATUS hif_bus_open(struct hif_softc *hif_sc,
 	case QDF_BUS_TYPE_PCI:
 		status = hif_initialize_pci_ops(hif_sc);
 		break;
+	case QDF_BUS_TYPE_IPCI:
+		status = hif_initialize_ipci_ops(hif_sc);
+		break;
 	case QDF_BUS_TYPE_SNOC:
 		status = hif_initialize_snoc_ops(&hif_sc->bus_ops);
 		break;

hif/src/dispatcher/multibus.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -122,6 +122,39 @@ static inline int hif_pci_get_context_size(void)
 }
 #endif /* HIF_PCI */
 
+#ifdef HIF_IPCI
+/**
+ * hif_initialize_ipci_ops() - initialize the pci ops
+ * @hif_sc: pointer to hif context
+ *
+ * Return: QDF_STATUS_SUCCESS
+ */
+QDF_STATUS hif_initialize_ipci_ops(struct hif_softc *hif_sc);
+
+/**
+ * hif_ipci_get_context_size() - return the size of the ipci context
+ *
+ * Return the size of the context.  (0 for invalid bus)
+ */
+int hif_ipci_get_context_size(void);
+#else
+static inline QDF_STATUS hif_initialize_ipci_ops(struct hif_softc *hif_sc)
+{
+	HIF_ERROR("%s: not supported", __func__);
+	return QDF_STATUS_E_NOSUPPORT;
+}
+
+/**
+ * hif_ipci_get_context_size() - dummy when ipci isn't supported
+ *
+ * Return: 0 as an invalid size to indicate no support
+ */
+static inline int hif_ipci_get_context_size(void)
+{
+	return 0;
+}
+#endif /* HIF_IPCI */
+
 #ifdef HIF_AHB
 QDF_STATUS hif_initialize_ahb_ops(struct hif_bus_ops *bus_ops);
 int hif_ahb_get_context_size(void);

hif/src/dispatcher/multibus_ipci.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "hif.h"
+#include "hif_main.h"
+#include "multibus.h"
+#include "ipci_api.h"
+#include "hif_io32.h"
+#include "dummy.h"
+#include "ce_api.h"
+
+/**
+ * hif_initialize_ipci_ops() - initialize the pci ops
+ * @bus_ops: hif_bus_ops table pointer to initialize
+ *
+ * Return: QDF_STATUS_SUCCESS
+ */
+QDF_STATUS hif_initialize_ipci_ops(struct hif_softc *hif_sc)
+{
+	struct hif_bus_ops *bus_ops = &hif_sc->bus_ops;
+
+	bus_ops->hif_bus_open = &hif_ipci_open;
+	bus_ops->hif_bus_close = &hif_ipci_close;
+	bus_ops->hif_bus_prevent_linkdown = &hif_ipci_prevent_linkdown;
+	bus_ops->hif_reset_soc = &hif_dummy_reset_soc;
+	bus_ops->hif_bus_suspend = &hif_ipci_bus_suspend;
+	bus_ops->hif_bus_resume = &hif_ipci_bus_resume;
+	bus_ops->hif_bus_suspend_noirq = &hif_ipci_bus_suspend_noirq;
+	bus_ops->hif_bus_resume_noirq = &hif_ipci_bus_resume_noirq;
+	bus_ops->hif_target_sleep_state_adjust =
+		&hif_dummy_target_sleep_state_adjust;
+	bus_ops->hif_disable_isr = &hif_ipci_disable_isr;
+	bus_ops->hif_nointrs = &hif_ipci_nointrs;
+	bus_ops->hif_enable_bus = &hif_ipci_enable_bus;
+	bus_ops->hif_disable_bus = &hif_ipci_disable_bus;
+	bus_ops->hif_bus_configure = &hif_ipci_bus_configure;
+	bus_ops->hif_get_config_item = &hif_dummy_get_config_item;
+	bus_ops->hif_set_mailbox_swap = &hif_dummy_set_mailbox_swap;
+	bus_ops->hif_claim_device = &hif_dummy_claim_device;
+	bus_ops->hif_shutdown_device = &hif_ce_stop;
+	bus_ops->hif_stop = &hif_ce_stop;
+	bus_ops->hif_cancel_deferred_target_sleep =
+		&hif_dummy_cancel_deferred_target_sleep;
+	bus_ops->hif_irq_disable = &hif_dummy_irq_disable;
+	bus_ops->hif_irq_enable = &hif_dummy_irq_enable;
+	bus_ops->hif_dump_registers = &hif_ipci_dump_registers;
+	bus_ops->hif_dump_target_memory = &hif_ce_dump_target_memory;
+	bus_ops->hif_ipa_get_ce_resource = &hif_ce_ipa_get_ce_resource;
+	bus_ops->hif_mask_interrupt_call = &hif_dummy_mask_interrupt_call;
+	bus_ops->hif_enable_power_management =
+		&hif_ipci_enable_power_management;
+	bus_ops->hif_disable_power_management =
+		&hif_ipci_disable_power_management;
+	bus_ops->hif_grp_irq_configure = &hif_ipci_configure_grp_irq;
+	bus_ops->hif_display_stats =
+		&hif_ipci_display_stats;
+	bus_ops->hif_clear_stats =
+		&hif_ipci_clear_stats;
+	bus_ops->hif_addr_in_boundary = &hif_dummy_addr_in_boundary;
+	bus_ops->hif_needs_bmi = &hif_ipci_needs_bmi;
+
+	return QDF_STATUS_SUCCESS;
+}
+
+/**
+ * hif_ipci_get_context_size() - return the size of the ipci context
+ *
+ * Return the size of the context.  (0 for invalid bus)
+ */
+int hif_ipci_get_context_size(void)
+{
+	return sizeof(struct hif_ipci_softc);
+}

hif/src/hif_io32.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -23,7 +23,8 @@
 #include "hif.h"
 #include "hif_main.h"
 
-#if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
+#if defined(HIF_REG_WINDOW_SUPPORT) && (defined(HIF_PCI) || \
+    defined(HIF_IPCI))
 
 static inline
 void hif_write32_mb_reg_window(void *sc,
@@ -93,9 +94,14 @@ uint32_t hif_read32_mb_reg_window(void *sc,
 #endif
 #ifdef HIF_SNOC
 #include "hif_io32_snoc.h"
-#endif /* HIF_PCI */
+#endif
+#ifdef HIF_IPCI
+#include "hif_io32_ipci.h"
+#endif
+
+#if defined(HIF_REG_WINDOW_SUPPORT) && (defined(HIF_PCI) || \
+    defined(HIF_IPCI))
 
-#if defined(HIF_REG_WINDOW_SUPPORT) && defined(HIF_PCI)
 #include "qdf_lock.h"
 #include "qdf_util.h"
 

hif/src/hif_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -30,7 +30,8 @@
 #include <a_debug.h>
 #include "hif_main.h"
 #include "hif_hw_version.h"
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if (defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+     defined(HIF_IPCI))
 #include "ce_tasklet.h"
 #include "ce_api.h"
 #endif
@@ -498,9 +499,10 @@ void hif_close(struct hif_opaque_softc *hif_ctx)
 	qdf_mem_free(scn);
 }
 
-#if defined(QCA_WIFI_QCA8074) || defined(QCA_WIFI_QCA6018) || \
-	defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCA6390) || \
-	defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6490)
+#if (defined(QCA_WIFI_QCA8074) || defined(QCA_WIFI_QCA6018) || \
+     defined(QCA_WIFI_QCA6290) || defined(QCA_WIFI_QCA6390) || \
+     defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6490) || \
+     defined(QCA_WIFI_QCA6750))
 static QDF_STATUS hif_hal_attach(struct hif_softc *scn)
 {
 	if (ce_srng_based(scn)) {
@@ -857,6 +859,13 @@ int hif_get_device_type(uint32_t device_id,
 		HIF_INFO(" *********** QCA6490 *************\n");
 		break;
 
+	case QCA6750_DEVICE_ID:
+	case QCA6750_EMULATION_DEVICE_ID:
+		*hif_type = HIF_TYPE_QCA6750;
+		*target_type = TARGET_TYPE_QCA6750;
+		HIF_INFO(" *********** QCA6750 *************\n");
+		break;
+
 	case QCA8074V2_DEVICE_ID:
 		*hif_type = HIF_TYPE_QCA8074V2;
 		*target_type = TARGET_TYPE_QCA8074V2;
@@ -1116,7 +1125,8 @@ bool hif_is_recovery_in_progress(struct hif_softc *scn)
 	return false;
 }
 
-#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
+#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) || \
+    defined(HIF_IPCI)
 
 /**
  * hif_update_pipe_callback() - API to register pipe specific callbacks

hif/src/hif_main.h

@@ -92,6 +92,10 @@
 #define QCA6490_EMULATION_DEVICE_ID (0x010a)
 #define QCA6490_DEVICE_ID (0x1103)
 
+/* TODO: change IDs for Moselle */
+#define QCA6750_EMULATION_DEVICE_ID (0x010c)
+#define QCA6750_DEVICE_ID (0x1105)
+
 #define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
 #define AR9887_DEVICE_ID    (0x0050)
 #define AR900B_DEVICE_ID    (0x0040)
@@ -121,6 +125,7 @@
 #define RUMIM2M_DEVICE_ID_NODE5	0xaa11
 
 #define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
+#define HIF_GET_IPCI_SOFTC(scn) ((struct hif_ipci_softc *)scn)
 #define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)
 #define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn)
 #define HIF_GET_USB_SOFTC(scn) ((struct hif_usb_softc *)scn)

hif/src/qca6750def.c

@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#if defined(QCA6750_HEADERS_DEF)
+
+#undef UMAC
+#define WLAN_HEADERS 1
+#include "lithium_top_reg.h"
+#include "wfss_ce_reg_seq_hwioreg.h"
+#include "wcss_version.h"
+
+#define MISSING 0
+
+#define SOC_RESET_CONTROL_OFFSET MISSING
+#define GPIO_PIN0_OFFSET                        MISSING
+#define GPIO_PIN1_OFFSET                        MISSING
+#define GPIO_PIN0_CONFIG_MASK                   MISSING
+#define GPIO_PIN1_CONFIG_MASK                   MISSING
+#define LOCAL_SCRATCH_OFFSET 0x18
+#define GPIO_PIN10_OFFSET MISSING
+#define GPIO_PIN11_OFFSET MISSING
+#define GPIO_PIN12_OFFSET MISSING
+#define GPIO_PIN13_OFFSET MISSING
+#define MBOX_BASE_ADDRESS MISSING
+#define INT_STATUS_ENABLE_ERROR_LSB MISSING
+#define INT_STATUS_ENABLE_ERROR_MASK MISSING
+#define INT_STATUS_ENABLE_CPU_LSB MISSING
+#define INT_STATUS_ENABLE_CPU_MASK MISSING
+#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
+#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define INT_STATUS_ENABLE_ADDRESS MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define HOST_INT_STATUS_ADDRESS MISSING
+#define CPU_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
+#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
+#define COUNT_DEC_ADDRESS MISSING
+#define HOST_INT_STATUS_CPU_MASK MISSING
+#define HOST_INT_STATUS_CPU_LSB MISSING
+#define HOST_INT_STATUS_ERROR_MASK MISSING
+#define HOST_INT_STATUS_ERROR_LSB MISSING
+#define HOST_INT_STATUS_COUNTER_MASK MISSING
+#define HOST_INT_STATUS_COUNTER_LSB MISSING
+#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
+#define WINDOW_DATA_ADDRESS MISSING
+#define WINDOW_READ_ADDR_ADDRESS MISSING
+#define WINDOW_WRITE_ADDR_ADDRESS MISSING
+/* GPIO Register */
+#define GPIO_ENABLE_W1TS_LOW_ADDRESS            MISSING
+#define GPIO_PIN0_CONFIG_LSB                    MISSING
+#define GPIO_PIN0_PAD_PULL_LSB                  MISSING
+#define GPIO_PIN0_PAD_PULL_MASK                 MISSING
+/* SI reg */
+#define SI_CONFIG_ERR_INT_MASK                  MISSING
+#define SI_CONFIG_ERR_INT_LSB                   MISSING
+
+#define RTC_SOC_BASE_ADDRESS MISSING
+#define RTC_WMAC_BASE_ADDRESS MISSING
+#define SOC_CORE_BASE_ADDRESS MISSING
+#define WLAN_MAC_BASE_ADDRESS MISSING
+#define GPIO_BASE_ADDRESS MISSING
+#define ANALOG_INTF_BASE_ADDRESS MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define CE_COUNT		12
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define SI_BASE_ADDRESS MISSING
+#define DRAM_BASE_ADDRESS MISSING
+
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
+#define CLOCK_CONTROL_OFFSET MISSING
+#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
+#define RESET_CONTROL_SI0_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_OFFSET MISSING
+#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
+#define CPU_CLOCK_OFFSET MISSING
+
+#define CPU_CLOCK_STANDARD_LSB MISSING
+#define CPU_CLOCK_STANDARD_MASK MISSING
+#define LPO_CAL_ENABLE_LSB MISSING
+#define LPO_CAL_ENABLE_MASK MISSING
+#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
+
+#define SOC_CHIP_ID_ADDRESS	  MISSING
+#define SOC_CHIP_ID_REVISION_MASK MISSING
+#define SOC_CHIP_ID_REVISION_LSB  MISSING
+#define SOC_CHIP_ID_REVISION_MSB  MISSING
+
+#define FW_IND_EVENT_PENDING MISSING
+#define FW_IND_INITIALIZED MISSING
+
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
+
+#define SR_WR_INDEX_ADDRESS MISSING
+#define DST_WATERMARK_ADDRESS MISSING
+
+#define DST_WR_INDEX_ADDRESS MISSING
+#define SRC_WATERMARK_ADDRESS MISSING
+#define SRC_WATERMARK_LOW_MASK MISSING
+#define SRC_WATERMARK_HIGH_MASK MISSING
+#define DST_WATERMARK_LOW_MASK MISSING
+#define DST_WATERMARK_HIGH_MASK MISSING
+#define CURRENT_SRRI_ADDRESS MISSING
+#define CURRENT_DRRI_ADDRESS MISSING
+#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_ADDRESS MISSING
+#define MISC_IS_ADDRESS MISSING
+#define HOST_IS_COPY_COMPLETE_MASK MISSING
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
+
+#define HOST_IE_ADDRESS HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR
+#define HOST_IE_ADDRESS_2 HWIO_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR
+
+#define HOST_IE_COPY_COMPLETE_MASK MISSING
+#define SR_BA_ADDRESS MISSING
+#define SR_BA_ADDRESS_HIGH MISSING
+#define SR_SIZE_ADDRESS MISSING
+#define CE_CTRL1_ADDRESS MISSING
+#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
+#define DR_BA_ADDRESS MISSING
+#define DR_BA_ADDRESS_HIGH MISSING
+#define DR_SIZE_ADDRESS MISSING
+#define CE_CMD_REGISTER MISSING
+#define CE_MSI_ADDRESS MISSING
+#define CE_MSI_ADDRESS_HIGH MISSING
+#define CE_MSI_DATA MISSING
+#define CE_MSI_ENABLE_BIT MISSING
+#define MISC_IE_ADDRESS MISSING
+#define MISC_IS_AXI_ERR_MASK MISSING
+#define MISC_IS_DST_ADDR_ERR_MASK MISSING
+#define MISC_IS_SRC_LEN_ERR_MASK MISSING
+#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
+#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
+#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
+#define SRC_WATERMARK_LOW_LSB MISSING
+#define SRC_WATERMARK_HIGH_LSB MISSING
+#define DST_WATERMARK_LOW_LSB MISSING
+#define DST_WATERMARK_HIGH_LSB MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
+#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
+#define CE_WRAPPER_DEBUG_OFFSET MISSING
+#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
+#define CE_DEBUG_OFFSET MISSING
+#define CE_DEBUG_SEL_MSB MISSING
+#define CE_DEBUG_SEL_LSB MISSING
+#define CE_DEBUG_SEL_MASK MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
+
+#define QCA6750_BOARD_DATA_SZ MISSING
+#define QCA6750_BOARD_EXT_DATA_SZ MISSING
+
+#define MY_TARGET_DEF QCA6750_TARGETdef
+#define MY_HOST_DEF QCA6750_HOSTdef
+#define MY_CEREG_DEF QCA6750_CE_TARGETdef
+#define MY_TARGET_BOARD_DATA_SZ QCA6750_BOARD_DATA_SZ
+#define MY_TARGET_BOARD_EXT_DATA_SZ QCA6750_BOARD_EXT_DATA_SZ
+#include "targetdef.h"
+#include "hostdef.h"
+#else
+#include "common_drv.h"
+#include "targetdef.h"
+#include "hostdef.h"
+struct targetdef_s *QCA6750_TARGETdef;
+struct hostdef_s *QCA6750_HOSTdef;
+#endif /*QCA6750_HEADERS_DEF */

hif/src/regtable.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -150,6 +150,13 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
 		break;
 #endif /* QCA6490_HEADERS_DEF */
 
+#if defined(QCA6750_HEADERS_DEF)
+	case TARGET_TYPE_QCA6750:
+		scn->targetdef = QCA6750_TARGETdef;
+		scn->target_ce_def = QCA6750_CE_TARGETdef;
+		HIF_TRACE("%s: TARGET_TYPE_QCA6750", __func__);
+		break;
+#endif /* QCA6750_HEADERS_DEF */
 	default:
 		break;
 	}
@@ -258,6 +265,12 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
 		break;
 #endif /* QCA6490_HEADERS_DEF */
 
+#if defined(QCA6750_HEADERS_DEF)
+	case TARGET_TYPE_QCA6750:
+		scn->hostdef = QCA6750_HOSTdef;
+		HIF_TRACE("%s: TARGET_TYPE_QCA6750", __func__);
+			break;
+#endif /* QCA6750_HEADERS_DEF */
 	default:
 		break;
 	}