disp: msm: dsi: enable DMA start window scheduling for broadcast commands

As per the HW requirements it is highly recommended to use DMA start window
to trigger broadcast commands. If not used then it can result in a hardware
hang with the DSI controllers going out of sync. This behavior is even more
prominent in cases of higher refresh rates.

Currently, reset_trigger_controls is called as part of next command.
Due to this, when unicast command is sent after broadcast command,
reset_trigger_controls does not get called for slave controller,
leading to issues.

As part of this change, DMA start window scheduling is enabled as default
for broadcast commands and reset_trigger_controls is done as part of
post_cmd_transfer operations.

Change-Id: I2402214ed79b376d102b88d4f7e6a06fcb5712d3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Tento commit je obsažen v:
Ritesh Kumar
2021-12-23 16:25:13 +05:30
rodič 4cc5b3cabb
revize fd2dc5be06
2 změnil soubory, kde provedl 12 přidání a 5 odebrání

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@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/ */
@@ -422,6 +423,7 @@ static void dsi_ctrl_clear_dma_status(struct dsi_ctrl *dsi_ctrl)
static void dsi_ctrl_post_cmd_transfer(struct dsi_ctrl *dsi_ctrl) static void dsi_ctrl_post_cmd_transfer(struct dsi_ctrl *dsi_ctrl)
{ {
int rc = 0; int rc = 0;
struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops;
struct dsi_clk_ctrl_info clk_info; struct dsi_clk_ctrl_info clk_info;
u32 mask = BIT(DSI_FIFO_OVERFLOW); u32 mask = BIT(DSI_FIFO_OVERFLOW);
@@ -438,6 +440,10 @@ static void dsi_ctrl_post_cmd_transfer(struct dsi_ctrl *dsi_ctrl)
dsi_ctrl_dma_cmd_wait_for_done(dsi_ctrl); dsi_ctrl_dma_cmd_wait_for_done(dsi_ctrl);
} }
if (dsi_ctrl->hw.reset_trig_ctrl)
dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
&dsi_ctrl->host_config.common_config);
/* Command engine disable, unmask overflow, remove vote on clocks and gdsc */ /* Command engine disable, unmask overflow, remove vote on clocks and gdsc */
rc = dsi_ctrl_set_cmd_engine_state(dsi_ctrl, DSI_CTRL_ENGINE_OFF, false); rc = dsi_ctrl_set_cmd_engine_state(dsi_ctrl, DSI_CTRL_ENGINE_OFF, false);
if (rc) if (rc)
@@ -1377,10 +1383,6 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags, SDE_EVT32(dsi_ctrl->cell_index, SDE_EVTLOG_FUNC_ENTRY, flags,
msg->flags); msg->flags);
if (dsi_ctrl->hw.reset_trig_ctrl)
dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
&dsi_ctrl->host_config.common_config);
if (dsi_hw_ops.splitlink_cmd_setup && split_link->enabled) if (dsi_hw_ops.splitlink_cmd_setup && split_link->enabled)
dsi_hw_ops.splitlink_cmd_setup(&dsi_ctrl->hw, dsi_hw_ops.splitlink_cmd_setup(&dsi_ctrl->hw,
&dsi_ctrl->host_config.common_config, flags); &dsi_ctrl->host_config.common_config, flags);

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@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/ */
@@ -704,14 +705,18 @@ static void dsi_display_set_cmd_tx_ctrl_flags(struct dsi_display *display,
/* /*
* Set flags for command scheduling. * Set flags for command scheduling.
* 1) In video mode command DMA scheduling is default. * 1) In video mode command DMA scheduling is default.
* 2) In command mode command DMA scheduling depends on message * 2) In command mode unicast command DMA scheduling depends on message
* flag and TE needs to be running. * flag and TE needs to be running.
* 3) In command mode broadcast command DMA scheduling is default and
* TE needs to be running.
*/ */
if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) { if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) {
flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED; flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
} else { } else {
if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED) if (msg->flags & MIPI_DSI_MSG_CMD_DMA_SCHED)
flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED; flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
if (flags & DSI_CTRL_CMD_BROADCAST)
flags |= DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
if (!display->enabled) if (!display->enabled)
flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED; flags &= ~DSI_CTRL_CMD_CUSTOM_DMA_SCHED;
} }