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disp: msm: dsi: update DSI PHY configuration to support splitlink

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Change updates DSI PHY programming sequence for splitlink configuration.

Change-Id: I708cf83717c6f640c918d41cc122794a10f979ba
Signed-off-by: Vara Reddy <varar@codeaurora.org>
This commit is contained in:
Vara Reddy
2021-02-10 20:02:52 -08:00
parent 142bb24d7c
commit fcb3849c69
4 changed files with 56 additions and 5 deletions
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2
msm/dsi/dsi_phy_hw.h
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@@ -116,6 +116,7 @@ struct dsi_phy_per_lane_cfgs {
* @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
* @phy_type: Phy-type (Dphy/Cphy).
* @bit_clk_rate_hz: DSI bit clk rate in HZ.
* @split_link: DSI split link config data.
*/
struct dsi_phy_cfg {
struct dsi_phy_per_lane_cfgs lanecfg;
@@ -128,6 +129,7 @@ struct dsi_phy_cfg {
bool force_clk_lane_hs;
enum dsi_phy_type phy_type;
unsigned long bit_clk_rate_hz;
struct dsi_split_link_config split_link;
};
struct dsi_phy_hw;