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qcacmn: Initial Hal changes for QCA5332

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Changes to create hal files and add hal related changes in hal_srng.c

Change-Id: I96dd76333e68bdd030e17e09602b93843ebc5030
CRs-Fixed: 3233322
This commit is contained in:
Hariharan Ramanathan
2022-06-29 11:46:58 +05:30
committed by Madan Koyyalamudi
parent d8c841f63b
commit fc00c5bb21
4 changed files with 3097 additions and 0 deletions
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10
hal/wifi3.0/hal_srng.c
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@@ -58,6 +58,9 @@ void hal_qca6750_attach(struct hal_soc *hal);
#ifdef QCA_WIFI_QCA5018
void hal_qca5018_attach(struct hal_soc *hal);
#endif
#ifdef QCA_WIFI_QCA5332
void hal_qca5332_attach(struct hal_soc *hal);
#endif
#ifdef QCA_WIFI_KIWI
void hal_kiwi_attach(struct hal_soc *hal);
#endif
@@ -505,6 +508,13 @@ static void hal_target_based_configure(struct hal_soc *hal)
hal->static_window_map = true;
hal_qcn9224_attach(hal);
break;
#endif
#ifdef QCA_WIFI_QCA5332
case TARGET_TYPE_QCA5332:
hal->use_register_windowing = true;
hal->static_window_map = true;
hal_qca5332_attach(hal);
break;
#endif
default:
break;

2523
hal/wifi3.0/qca5332/hal_5332.c Normal file
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File diff suppressed because it is too large Load Diff

109
hal/wifi3.0/qca5332/hal_5332_rx.h Normal file
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@@ -0,0 +1,109 @@
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_5332_RX_H_
#define _HAL_5332_RX_H_
#include "qdf_util.h"
#include "qdf_types.h"
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "tcl_data_cmd.h"
#include "phyrx_rssi_legacy.h"
#include "rx_msdu_start.h"
#include "tlv_tag_def.h"
#include "hal_hw_headers.h"
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"
#include "phyrx_other_receive_info_ru_details.h"
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
(uint8_t *)(link_desc_va) + \
RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
(uint8_t *)(msdu0) + \
RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
(uint8_t *)(ent_ring_desc) + \
RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
(uint8_t *)(dst_ring_desc) + \
REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
do { \
reg_val &= \
~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
reg_val |= \
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
AGING_LIST_ENABLE, 1) | \
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
AGING_FLUSH_ENABLE, 1); \
HAL_REG_WRITE(soc, \
HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
REO_REG_REG_BASE), \
reg_val); \
reg_val = HAL_REG_READ(soc, \
HWIO_REO_R0_MISC_CTL_ADDR( \
REO_REG_REG_BASE)); \
reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
FRAGMENT_DEST_RING, \
(reo_params)->frag_dst_ring); \
} while (0)
#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
((struct rx_msdu_desc_info *) \
_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
#define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy
#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
((struct rx_msdu_details *) \
_OFFSET_TO_BYTE_PTR((link_desc),\
RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
#define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
((HAL_RX_GET((rx_tlv), \
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
RTT_CFR_STATUS) & \
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
#endif
#endif

455
hal/wifi3.0/qca5332/hal_5332_tx.h Normal file
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@@ -0,0 +1,455 @@
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
*/
#ifndef _HAL_5332_TX_H_
#define _HAL_5332_TX_H_
#include "tcl_data_cmd.h"
#include "phyrx_rssi_legacy.h"
#include "hal_internal.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_tx.h"
#include "hal_api_mon.h"
#include <hal_be_tx.h>
#define DSCP_TID_TABLE_SIZE 24
#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
/**
* hal_tx_set_dscp_tid_map_5332() - Configure default DSCP to TID map table
* @soc: HAL SoC context
* @map: DSCP-TID mapping table
* @id: mapping table ID - 0-31
*
* DSCP are mapped to 8 TID values using TID values programmed
* in any of the 32 DSCP_TID_MAPS (id = 0-31).
*
* Return: none
*/
static void hal_tx_set_dscp_tid_map_5332(struct hal_soc *hal_soc, uint8_t *map,
uint8_t id)
{
int i;
uint32_t addr, cmn_reg_addr;
uint32_t value = 0, regval;
uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
struct hal_soc *soc = (struct hal_soc *)hal_soc;
if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
return;
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
MAC_TCL_REG_REG_BASE);
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
MAC_TCL_REG_REG_BASE,
id * NUM_WORDS_PER_DSCP_TID_TABLE);
/* Enable read/write access */
regval = HAL_REG_READ(soc, cmn_reg_addr);
regval |=
(1 <<
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
/* Write 8 (24 bits) DSCP-TID mappings in each interation */
for (i = 0; i < 64; i += 8) {
value = (map[i] |
(map[i + 1] << 0x3) |
(map[i + 2] << 0x6) |
(map[i + 3] << 0x9) |
(map[i + 4] << 0xc) |
(map[i + 5] << 0xf) |
(map[i + 6] << 0x12) |
(map[i + 7] << 0x15));
qdf_mem_copy(&val[cnt], (void *)&value, 3);
cnt += 3;
}
for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
regval = *(uint32_t *)(val + i);
HAL_REG_WRITE(soc, addr,
(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
addr += 4;
}
/* Diasble read/write access */
regval = HAL_REG_READ(soc, cmn_reg_addr);
regval &=
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
}
/**
* hal_tx_update_dscp_tid_5332() - Update the dscp tid map table as updated
* by the user
* @soc: HAL SoC context
* @map: DSCP-TID mapping table
* @id : MAP ID
* @dscp: DSCP_TID map index
*
* Return: void
*/
static void hal_tx_update_dscp_tid_5332(struct hal_soc *soc, uint8_t tid,
uint8_t id, uint8_t dscp)
{
uint32_t addr, addr1, cmn_reg_addr;
uint32_t start_value = 0, end_value = 0;
uint32_t regval;
uint8_t end_bits = 0;
uint8_t start_bits = 0;
uint32_t start_index, end_index;
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
MAC_TCL_REG_REG_BASE);
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
MAC_TCL_REG_REG_BASE,
id * NUM_WORDS_PER_DSCP_TID_TABLE);
start_index = dscp * HAL_TX_BITS_PER_TID;
end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
% HAL_TX_NUM_DSCP_REGISTER_SIZE;
start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
HAL_TX_NUM_DSCP_REGISTER_SIZE));
if (end_index < start_index) {
end_bits = end_index + 1;
start_bits = HAL_TX_BITS_PER_TID - end_bits;
start_value = tid << start_index;
end_value = tid >> start_bits;
addr1 = addr + 4;
} else {
start_bits = HAL_TX_BITS_PER_TID - end_bits;
start_value = tid << start_index;
addr1 = 0;
}
/* Enable read/write access */
regval = HAL_REG_READ(soc, cmn_reg_addr);
regval |=
(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
regval = HAL_REG_READ(soc, addr);
if (end_index < start_index)
regval &= (~0) >> start_bits;
else
regval &= ~(7 << start_index);
regval |= start_value;
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
if (addr1) {
regval = HAL_REG_READ(soc, addr1);
regval &= (~0) << end_bits;
regval |= end_value;
HAL_REG_WRITE(soc, addr1, (regval &
HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
}
/* Diasble read/write access */
regval = HAL_REG_READ(soc, cmn_reg_addr);
regval &=
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
}
/**
* hal_tx_init_cmd_credit_ring_5332() - Initialize command/credit SRNG
* @hal_soc_hdl: Handle to HAL SoC structure
* @hal_srng: Handle to HAL SRNG structure
*
* Return: none
*/
static inline void
hal_tx_init_cmd_credit_ring_5332(hal_soc_handle_t hal_soc_hdl,
hal_ring_handle_t hal_ring_hdl)
{
}
/* TX MONITOR */
#ifdef QCA_MONITOR_2_0_SUPPORT
#if defined(TX_MONITOR_WORD_MASK)
typedef struct tx_fes_setup_compact_5332 hal_tx_fes_setup_t;
struct tx_fes_setup_compact_5332 {
/* DWORD - 0 */
uint32_t schedule_id;
/* DWORD - 1 */
uint32_t reserved_1a : 7, // [0: 6]
transmit_start_reason : 3, // [7: 9]
reserved_1b : 13, // [10: 22]
number_of_users : 6, // [28: 23]
MU_type : 1, // [29]
reserved_1c : 2; // [30]
/* DWORD - 2 */
uint32_t reserved_2a : 4, // [0: 3]
ndp_frame : 2, // [4: 5]
txbf : 1, // [6]
reserved_2b : 3, // [7: 9]
static_bandwidth : 3, // [12: 10]
reserved_2c : 1, // [13]
transmission_contains_MU_RTS : 1, // [14]
reserved_2d : 17; // [15: 31]
/* DWORD - 3 */
uint32_t reserved_3a : 15, // [0: 14]
mu_ndp : 1, // [15]
reserved_3b : 11, // [16: 26]
ndpa : 1, // [27]
reserved_3c : 4; // [28: 31]
};
#endif
#endif /* QCA_MONITOR_2_0_SUPPORT */
/**
* hal_tx_set_ppe_cmn_config_5332() - Set the PPE common config register
* @hal_soc_hdl: HAL SoC handle
* @cmn_cfg: Common PPE config
*
* Based on the PPE2TCL descriptor below errors, if the below register
* values are set then the packets are forward to Tx rule handler if 1'0b
* or to TCL exit base if 1'1b.
*
* Return: void
*/
static inline
void hal_tx_set_ppe_cmn_config_5332(hal_soc_handle_t hal_soc_hdl,
union hal_tx_cmn_config_ppe *cmn_cfg)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
union hal_tx_cmn_config_ppe *cfg =
(union hal_tx_cmn_config_ppe *)cmn_cfg;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
reg_val |=
(cfg->drop_prec_err &
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
reg_val |=
(cfg->fake_mac_hdr &
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
reg_val |=
(cfg->cpu_code_inv &
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
reg_val |=
(cfg->l3_l4_err &
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_vp_entry_5332() - Set the PPE VP entry
* @hal_soc_hdl: HAL SoC handle
* @vp_cfg: PPE VP config
* @ppe_vp_idx : PPE VP index to the table
*
* Return: void
*/
static inline
void hal_tx_set_ppe_vp_entry_5332(hal_soc_handle_t hal_soc_hdl,
union hal_tx_ppe_vp_config *cfg,
int ppe_vp_idx)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
ppe_vp_idx);
/*
* Drop precedence is enabled by default.
*/
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK;
reg_val |= (cfg->vp_num &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK;
reg_val |= (cfg->pmac_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK;
reg_val |= (cfg->bank_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK;
reg_val |= (cfg->vdev_id &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK;
reg_val |=
(cfg->search_idx_reg_num &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT;
reg_val &=
~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
reg_val |=
(cfg->use_ppe_int_pri &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK;
reg_val |= (cfg->to_fw &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT;
reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK;
reg_val |= (cfg->drop_prec_enable &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_pri2tid_map1_5332()
* @hal_soc_hdl: HAL SoC handle
* @val : PRI to TID value
* @map_no: Map number
*
* Return: void
*/
static inline
void hal_tx_set_ppe_pri2tid_map_5332(hal_soc_handle_t hal_soc_hdl,
uint32_t val, uint8_t map_no)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
if (map_no == 0)
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
else
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
reg_val |= val;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_set_ppe_pri2tid_map1_5332()
* @hal_soc_hdl: HAL SoC handle
* @val : PRI to TID value
* @map_no: Map number
*
* Return: void
*/
static inline
void hal_tx_enable_pri2tid_map_5332(hal_soc_handle_t hal_soc_hdl,
bool val, uint8_t ppe_vp_idx)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0;
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
ppe_vp_idx);
/*
* Drop precedence is enabled by default.
*/
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &=
~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
reg_val |=
(val &
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
/**
* hal_tx_update_ppe_pri2tid_5332()
* @hal_soc_hdl: HAL SoC handle
* @pri: INT_PRI
* @tid: Wi-Fi TID
*
* Return: void
*/
static inline
void hal_tx_update_ppe_pri2tid_5332(hal_soc_handle_t hal_soc_hdl,
uint8_t pri, uint8_t tid)
{
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
uint32_t reg_addr, reg_val = 0, mask, shift;
/*
* INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
* is in MAP1 register.
*/
switch (pri) {
case 0 ... 9:
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
mask =
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
break;
case 10 ... 15:
pri = pri - 10;
reg_addr =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
mask =
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
shift =
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
break;
default:
return;
}
reg_val = HAL_REG_READ(soc, reg_addr);
reg_val &= ~mask;
reg_val |= (pri << shift) & mask;
HAL_REG_WRITE(soc, reg_addr, reg_val);
}
#endif /* _HAL_5332_TX_H_ */