Merge "disp: msm: sde: reset dsc mux config in encoder disable"
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fba8cf7c57
@@ -3188,6 +3188,7 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
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struct sde_encoder_virt *sde_enc;
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struct sde_encoder_virt *sde_enc;
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struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
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struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
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struct sde_ctl_flush_cfg cfg;
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struct sde_ctl_flush_cfg cfg;
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struct sde_hw_dsc *hw_dsc = NULL;
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int i;
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int i;
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ctl->ops.reset(ctl);
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ctl->ops.reset(ctl);
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@@ -3242,6 +3243,17 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
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phys_enc->hw_pp->merge_3d ?
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phys_enc->hw_pp->merge_3d ?
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phys_enc->hw_pp->merge_3d->idx : 0);
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phys_enc->hw_pp->merge_3d->idx : 0);
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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hw_dsc = sde_enc->hw_dsc[i];
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if (hw_dsc && hw_dsc->ops.bind_pingpong_blk) {
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hw_dsc->ops.bind_pingpong_blk(hw_dsc, false, PINGPONG_MAX);
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if (ctl->ops.update_bitmask)
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ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_DSC, hw_dsc->idx, true);
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}
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}
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sde_crtc_disable_cp_features(sde_enc->base.crtc);
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sde_crtc_disable_cp_features(sde_enc->base.crtc);
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ctl->ops.get_pending_flush(ctl, &cfg);
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ctl->ops.get_pending_flush(ctl, &cfg);
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SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);
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SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);
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@@ -24,6 +24,9 @@
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(((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
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(((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id)) ||\
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((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
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((h)->rsvp_nxt && ((h)->rsvp_nxt->enc_id != (r)->enc_id)))
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#define RESERVED_BY_CURRENT(h, r) \
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(((h)->rsvp && ((h)->rsvp->enc_id == (r)->enc_id)))
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#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
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#define RM_RQ_LOCK(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_LOCK))
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#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
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#define RM_RQ_CLEAR(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_RESERVE_CLEAR))
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#define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
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#define RM_RQ_DSPP(r) ((r)->top_ctrl & BIT(SDE_RM_TOPCTL_DSPP))
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@@ -1848,12 +1851,39 @@ static int _sde_rm_make_ctl_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
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return ret;
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return ret;
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}
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}
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/*
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* Returns number of dsc hw blocks previously owned by this encoder.
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* Returns 0 if not found or error
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*/
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static int _sde_rm_find_prev_dsc(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
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u8 *prev_dsc, u32 max_cnt)
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{
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int i = 0;
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struct sde_rm_hw_iter iter_dsc;
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if ((!prev_dsc) || (max_cnt < MAX_DATA_PATH_PER_DSIPLAY))
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return 0;
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sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
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while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
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if (RESERVED_BY_CURRENT(iter_dsc.blk, rsvp))
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prev_dsc[i++] = iter_dsc.blk->id;
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if (i >= MAX_DATA_PATH_PER_DSIPLAY)
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return 0;
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}
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return i;
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}
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static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
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static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
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struct sde_rm_requirements *reqs,
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struct sde_rm_requirements *reqs,
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struct sde_splash_display *splash_display)
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struct sde_splash_display *splash_display)
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{
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{
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int i;
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int i;
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u8 *hw_ids = NULL;
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u8 *hw_ids = NULL;
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u8 prev_dsc[MAX_DATA_PATH_PER_DSIPLAY] = {0,};
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/* Check if splash data provided dsc_ids */
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/* Check if splash data provided dsc_ids */
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if (splash_display) {
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if (splash_display) {
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@@ -1866,6 +1896,15 @@ static int _sde_rm_make_dsc_rsvp(struct sde_rm *rm, struct sde_rm_rsvp *rsvp,
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i, splash_display->dsc_ids[i]);
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i, splash_display->dsc_ids[i]);
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}
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}
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/*
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* find if this encoder has previously allocated dsc hw blocks, use same dsc blocks
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* if found to avoid switching dsc encoders during each modeset, as currently we
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* dont have feasible way of decoupling previously owned dsc blocks by resetting
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* respective dsc encoders mux control and flush them from commit path
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*/
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if (!hw_ids && _sde_rm_find_prev_dsc(rm, rsvp, prev_dsc, MAX_DATA_PATH_PER_DSIPLAY))
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return _sde_rm_reserve_dsc(rm, rsvp, reqs, prev_dsc);
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else
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return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
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return _sde_rm_reserve_dsc(rm, rsvp, reqs, hw_ids);
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}
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}
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