Merge "disp: msm: sde: add events to input and output hw-fences"

msm/sde/sde_crtc.c

@@ -3725,7 +3725,6 @@ static struct dma_fence *_sde_plane_get_input_hw_fence(struct drm_plane *plane)
 	struct dma_fence *input_hw_fence = NULL;
 	struct dma_fence_array *array = NULL;
 	struct dma_fence *spec_fence = NULL;
-	bool spec_hw_fence = true;
 	int i;
 
 	if (!plane || !plane->state) {
@@ -3741,6 +3740,8 @@ static struct dma_fence *_sde_plane_get_input_hw_fence(struct drm_plane *plane)
 		fence = (struct dma_fence *)pstate->input_fence;
 
 		if (test_bit(SPEC_FENCE_FLAG_FENCE_ARRAY, &fence->flags)) {
+			bool spec_hw_fence = false;
+
 			array = container_of(fence, struct dma_fence_array, base);
 			if (IS_ERR_OR_NULL(array))
 				goto exit;
@@ -3751,9 +3752,18 @@ static struct dma_fence *_sde_plane_get_input_hw_fence(struct drm_plane *plane)
 
 			for (i = 0; i < array->num_fences; i++) {
 				spec_fence = array->fences[i];
-				if (IS_ERR_OR_NULL(spec_fence) ||
-					!(test_bit(MSM_HW_FENCE_FLAG_ENABLED_BIT,
-						&spec_fence->flags))) {
+
+				if (!IS_ERR_OR_NULL(spec_fence) &&
+					test_bit(MSM_HW_FENCE_FLAG_ENABLED_BIT,
+						&spec_fence->flags)) {
+					spec_hw_fence = true;
+				} else {
+					/*
+					 * all child-fences of the spec fence must be hw-fences for
+					 * this fence to be considered hw-fence. Otherwise just
+					 * fail here to set the hw-fences and driver will use
+					 * sw-fences instead.
+					 */
 					spec_hw_fence = false;
 					break;
 				}

msm/sde/sde_encoder_phys_vid.c

@@ -963,7 +963,6 @@ static void sde_encoder_phys_vid_update_txq(struct sde_encoder_phys *phys_enc)
 	if (!sde_enc)
 		return;
 
-	SDE_EVT32(DRMID(phys_enc->parent));
 	sde_encoder_helper_update_out_fence_txq(sde_enc, true);
 }
 

msm/sde/sde_fence.c

@@ -302,10 +302,26 @@ int sde_fence_register_hw_fences_wait(struct sde_hw_ctl *hw_ctl, struct dma_fenc
 					dma_fence_get(array->fences[j]);
 					fence_list[fence_list_index++] = array->fences[j];
 				}
+
+				if (array->num_fences) /* print the first fence from array */
+					SDE_EVT32(ctl_id, num_fences, array->num_fences, i,
+						SDE_EVTLOG_H32(array->fences[0]->context),
+						SDE_EVTLOG_L32(array->fences[0]->context),
+						SDE_EVTLOG_H32(array->fences[0]->seqno),
+						SDE_EVTLOG_L32(array->fences[0]->seqno));
+				else
+					SDE_EVT32(ctl_id, num_fences, array->num_fences, i,
+						SDE_EVTLOG_ERROR);
+
 				/* remove refcount on parent */
 				dma_fence_put(fences[i]);
 			} else {
 				fence_list[fence_list_index++] = fences[i];
+
+				SDE_EVT32(ctl_id, num_fences, i, SDE_EVTLOG_H32(fences[i]->context),
+					SDE_EVTLOG_L32(fences[i]->context),
+					SDE_EVTLOG_H32(fences[i]->seqno),
+					SDE_EVTLOG_L32(fences[i]->seqno));
 			}
 		}
 
@@ -323,8 +339,17 @@ int sde_fence_register_hw_fences_wait(struct sde_hw_ctl *hw_ctl, struct dma_fenc
 		num_hw_fences = 1;
 
 	} else {
+		struct dma_fence_array *tmp_array;
+
 		hw_fences = fences;
 		num_hw_fences = num_fences;
+		tmp_array = dma_fence_is_array(fences[0]) ?
+				container_of(fences[0], struct dma_fence_array, base) :
+				NULL;
+		SDE_EVT32(ctl_id, num_hw_fences, SDE_EVTLOG_H32(fences[0]->context),
+			SDE_EVTLOG_L32(fences[0]->context), SDE_EVTLOG_H32(fences[0]->seqno),
+			SDE_EVTLOG_L32(fences[0]->seqno), fences[0]->flags,
+			tmp_array ? tmp_array->num_fences : SDE_EVTLOG_FUNC_CASE2);
 	}
 
 	/* register for wait */
@@ -482,6 +507,8 @@ int sde_fence_update_hw_fences_txq(struct sde_fence_context *ctx, bool vid_mode,
 		}
 
 		/* update hw-fence tx queue */
+		SDE_EVT32(ctl_id, SDE_EVTLOG_H32(fc->hwfence_index),
+			SDE_EVTLOG_L32(fc->hwfence_index));
 		ret = msm_hw_fence_update_txq(data->hw_fence_handle, fc->hwfence_index, 0, 0);
 		if (ret) {
 			SDE_ERROR("fail txq update index:%llu fctx:%llu seqno:%llu client:%d\n",

msm/sde_dbg.h

@@ -31,6 +31,9 @@
 #define SDE_EVTLOG_FATAL	0xbad
 #define SDE_EVTLOG_ERROR	0xebad
 
+#define SDE_EVTLOG_H32(val) (val >> 32)
+#define SDE_EVTLOG_L32(val) (val & 0xffffffff)
+
 /* flags to enable the HW block dumping */
 #define SDE_DBG_SDE		BIT(0)
 #define SDE_DBG_RSC		BIT(1)