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@@ -5506,6 +5506,44 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
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sde_cfg->demura_supported[SSPP_DMA3][0] = BIT(DEMURA_0) | BIT(DEMURA_2);
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sde_cfg->demura_supported[SSPP_DMA3][0] = BIT(DEMURA_0) | BIT(DEMURA_2);
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sde_cfg->demura_supported[SSPP_DMA3][1] = BIT(DEMURA_1);
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sde_cfg->demura_supported[SSPP_DMA3][1] = BIT(DEMURA_1);
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sde_cfg->has_line_insertion = true;
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sde_cfg->has_line_insertion = true;
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+ } else if (IS_VOLCANO_TARGET(hw_rev)) {
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+ set_bit(SDE_FEATURE_DEDICATED_CWB, sde_cfg->features);
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+ set_bit(SDE_FEATURE_CWB_DITHER, sde_cfg->features);
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+ set_bit(SDE_FEATURE_CWB_CROP, sde_cfg->features);
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+ set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
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+ set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
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+ set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
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+ set_bit(SDE_FEATURE_INLINE_SKIP_THRESHOLD, sde_cfg->features);
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+ set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
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+ set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
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+ set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
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+ set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
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+ set_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features);
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+ set_bit(SDE_FEATURE_FP16, sde_cfg->features);
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+ set_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &sde_cfg->mdp[0].features);
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+ set_bit(SDE_FEATURE_DEMURA, sde_cfg->features);
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+ set_bit(SDE_FEATURE_UBWC_STATS, sde_cfg->features);
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+ set_bit(SDE_FEATURE_HW_VSYNC_TS, sde_cfg->features);
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+ set_bit(SDE_FEATURE_AVR_STEP, sde_cfg->features);
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+ set_bit(SDE_FEATURE_VBIF_CLK_SPLIT, sde_cfg->features);
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+ set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
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+ set_bit(SDE_FEATURE_CTL_DONE, sde_cfg->features);
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+ set_bit(SDE_FEATURE_WB_ROTATION, sde_cfg->features);
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+ set_bit(SDE_FEATURE_EPT, sde_cfg->features);
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+ sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH;
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+ sde_cfg->autorefresh_disable_seq = AUTOREFRESH_DISABLE_SEQ2;
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+ /* if pingpong block supports it this should not be set on top block */
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+ sde_cfg->ppb_sz_program = SDE_PPB_SIZE_THRU_TOP;
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+ sde_cfg->perf.min_prefill_lines = 40;
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+ sde_cfg->vbif_qos_nlvl = 8;
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+ sde_cfg->qos_target_time_ns = 18600;
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+ sde_cfg->ts_prefill_rev = 2;
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+ sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
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+ sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_1;
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+ sde_cfg->sid_rev = SDE_SID_VERSION_2_0_0;
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+ sde_cfg->mdss_hw_block_size = 0x158;
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+ sde_cfg->demura_supported[SSPP_DMA1][0] = BIT(DEMURA_0);
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+ sde_cfg->has_line_insertion = true;
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} else if (IS_PITTI_TARGET(hw_rev)) {
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} else if (IS_PITTI_TARGET(hw_rev)) {
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set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
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set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
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sde_cfg->perf.min_prefill_lines = 40;
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sde_cfg->perf.min_prefill_lines = 40;
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