qcacmn: Trigger IRQ on Peregrine/swift by setting IRQ Bit of LF_TIMER 0

Set Interrupt bit of LF_TIMER 0 to induce interrupt on swift/peregrine Change-Id: I8a3941262dd7a4b19f8734b4017c9293fbb1b981
2018-09-06 12:43:36 +05:30
parent f9cf9461fd
commit fa1ddd5447
10 changed files with 71 additions and 11 deletions
--- a/hif/inc/reg_struct.h
+++ b/hif/inc/reg_struct.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -231,6 +231,7 @@ struct targetdef_s {
 	uint32_t d_CPU_INTR_ADDRESS;
 	uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
 	uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
+	uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;

 	/* chip id start */
 	uint32_t d_SI_CONFIG_ERR_INT_MASK;
--- a/hif/inc/regtable_pcie.h
+++ b/hif/inc/regtable_pcie.h
@@ -170,6 +170,8 @@
 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define SOC_LF_TIMER_STATUS0_ADDRESS \
+	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
 	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
--- a/hif/inc/target_reg_init.h
+++ b/hif/inc/target_reg_init.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -83,6 +83,10 @@ struct targetdef_s;
 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK        ATH_UNSUPPORTED_REG_OFFSET
 #endif

+#if !defined(SOC_LF_TIMER_STATUS0_ADDRESS)
+#define SOC_LF_TIMER_STATUS0_ADDRESS        ATH_UNSUPPORTED_REG_OFFSET
+#endif
+
 #if !defined(SOC_RESET_CONTROL_ADDRESS)
 #define SOC_RESET_CONTROL_ADDRESS    ATH_UNSUPPORTED_REG_OFFSET
 #define SOC_RESET_CONTROL_CE_RST_MASK    ATH_UNSUPPORTED_REG_OFFSET
@@ -290,6 +294,7 @@ static struct targetdef_s my_target_def = {
 	.d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS,
 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK
 		= SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	.d_SOC_LF_TIMER_STATUS0_ADDRESS = SOC_LF_TIMER_STATUS0_ADDRESS,
 	.d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK,
 	.d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB,
 	.d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS,
--- a/hif/src/adrastea_reg_def.h
+++ b/hif/src/adrastea_reg_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -1512,6 +1512,7 @@
 #define ADRASTEA_CPU_INTR_ADDRESS                            0xffffffff
 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
 #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
+#define ADRASTEA_SOC_LF_TIMER_STATUS0_ADDRESS                0xffffffff
 #define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \
 	(0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS)
 #define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
@@ -2023,6 +2024,8 @@ struct targetdef_s adrastea_targetdef = {
 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS,
 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
 		ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
+		ADRASTEA_SOC_LF_TIMER_STATUS0_ADDRESS,
 	/* chip id start */
 	.d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS,
 	.d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK,
--- a/hif/src/ar6320def.h
+++ b/hif/src/ar6320def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -204,6 +204,7 @@
 #define AR6320_CPU_INTR_ADDRESS                         0x0010
 #define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
 #define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
+#define AR6320_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
 #define AR6320_SOC_RESET_CONTROL_ADDRESS                0x00000000
 #define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
 #define AR6320_CORE_CTRL_ADDRESS                        0x0000
@@ -599,6 +600,8 @@ struct targetdef_s ar6320_targetdef = {
 		AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS,
 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
 		AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
+		AR6320_SOC_LF_TIMER_STATUS0_ADDRESS,

 	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
 	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
--- a/hif/src/ar6320v2def.h
+++ b/hif/src/ar6320v2def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -165,6 +165,7 @@
 #define AR6320V2_CPU_INTR_ADDRESS                         0x0010
 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
 #define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
+#define AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
 #define AR6320V2_SOC_RESET_CONTROL_ADDRESS                0x00000000
 #define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
 #define AR6320V2_CORE_CTRL_ADDRESS                        0x0000
@@ -645,6 +646,8 @@ struct targetdef_s ar6320v2_targetdef = {
 		AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
 		AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
+		AR6320V2_SOC_LF_TIMER_STATUS0_ADDRESS,
 	/* chip id start */
 	.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
 	.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
--- a/hif/src/ar9888def.h
+++ b/hif/src/ar9888def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2016, 2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -203,6 +203,7 @@
 #define AR9888_CPU_INTR_ADDRESS                         0x0010
 #define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
 #define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
+#define AR9888_SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
 #define AR9888_SOC_RESET_CONTROL_ADDRESS                0x00000000
 #define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
 #define AR9888_CORE_CTRL_ADDRESS                        0x0000
@@ -438,6 +439,8 @@ struct targetdef_s ar9888_targetdef = {
 		AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS,
 	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
 		AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	.d_SOC_LF_TIMER_STATUS0_ADDRESS =
+		AR9888_SOC_LF_TIMER_STATUS0_ADDRESS,
 };

 struct hostdef_s ar9888_hostdef = {
--- a/hif/src/pcie/if_pci.c
+++ b/hif/src/pcie/if_pci.c
@@ -3531,6 +3531,30 @@ end:
 	return 0;
 }

+/**
+ * hif_trigger_timer_irq() : Triggers interrupt on LF_Timer 0
+ * @scn: hif control structure
+ *
+ * Sets IRQ bit in LF Timer Status Address to awake peregrine/swift
+ * stuck at a polling loop in pcie_address_config in FW
+ *
+ * Return: none
+ */
+static void hif_trigger_timer_irq(struct hif_softc *scn)
+{
+	int tmp;
+	/* Trigger IRQ on Peregrine/Swift by setting
+	 * IRQ Bit of LF_TIMER 0
+	 */
+	tmp = hif_read32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS +
+						SOC_LF_TIMER_STATUS0_ADDRESS));
+	/* Set Raw IRQ Bit */
+	tmp |= 1;
+	/* SOC_LF_TIMER_STATUS0 */
+	hif_write32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS +
+		       SOC_LF_TIMER_STATUS0_ADDRESS), tmp);
+}
+
 /**
 * hif_target_sync() : ensure the target is ready
 * @scn: hif control structure
@@ -3560,7 +3584,9 @@ static void hif_target_sync(struct hif_softc *scn)
 	if (HAS_FW_INDICATOR) {
 		int wait_limit = 500;
 		int fw_ind = 0;
-
+		int retry_count = 0;
+		uint32_t target_type = scn->target_info.target_type;
+fw_retry:
 		HIF_TRACE("%s: Loop checking FW signal", __func__);
 		while (1) {
 			fw_ind = hif_read32_mb(scn, scn->mem +
@@ -3578,13 +3604,21 @@ static void hif_target_sync(struct hif_softc *scn)

 			qdf_mdelay(10);
 		}
-		if (wait_limit < 0)
+		if (wait_limit < 0) {
+			if (target_type == TARGET_TYPE_AR9888 &&
+			    retry_count++ < 2) {
+				hif_trigger_timer_irq(scn);
+				wait_limit = 500;
+				goto fw_retry;
+			}
 			HIF_TRACE("%s: FW signal timed out",
 					__func__);
-		else
+			qdf_assert_always(0);
+		} else {
 			HIF_TRACE("%s: Got FW signal, retries = %x",
 					__func__, 500-wait_limit);
 		}
+	}
 	hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS +
 			PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
 }
--- a/hif/src/sdio/regtable_sdio.h
+++ b/hif/src/sdio/regtable_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -197,6 +197,7 @@ struct targetdef_s {
 	uint32_t d_CPU_INTR_ADDRESS;
 	uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
 	uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
+	uint32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;

 	/* chip id start */
 	uint32_t d_SOC_CHIP_ID_ADDRESS;
@@ -361,6 +362,8 @@ struct targetdef_s {
 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define SOC_LF_TIMER_STATUS0_ADDRESS \
+	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)


 #define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
--- a/hif/src/usb/regtable_usb.h
+++ b/hif/src/usb/regtable_usb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
@@ -278,6 +278,7 @@ struct targetdef_s {
 	u_int32_t d_CPU_INTR_ADDRESS;
 	u_int32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
 	u_int32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
+	u_int32_t d_SOC_LF_TIMER_STATUS0_ADDRESS;
 	/* chip id start */
 	u_int32_t d_SOC_CHIP_ID_ADDRESS;
 	u_int32_t d_SOC_CHIP_ID_VERSION_MASK;
@@ -455,6 +456,8 @@ struct targetdef_s {
 		(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK  \
 		(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define SOC_LF_TIMER_STATUS0_ADDRESS      \
+		(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
 		(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
 #define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \