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qcacmn: Trigger IRQ on Peregrine/swift by setting IRQ Bit of LF_TIMER 0

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Set Interrupt bit of LF_TIMER 0 to induce interrupt on swift/peregrine

Change-Id: I8a3941262dd7a4b19f8734b4017c9293fbb1b981
This commit is contained in:
Sathyanarayanan Esakkiappan
2018-09-06 12:43:36 +05:30
committed by nshrivas
parent f9cf9461fd
commit fa1ddd5447
10 changed files with 71 additions and 11 deletions
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7
hif/inc/target_reg_init.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -83,6 +83,10 @@ struct targetdef_s;
#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET
#endif
#if !defined(SOC_LF_TIMER_STATUS0_ADDRESS)
#define SOC_LF_TIMER_STATUS0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
#endif
#if !defined(SOC_RESET_CONTROL_ADDRESS)
#define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET
#define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET
@@ -290,6 +294,7 @@ static struct targetdef_s my_target_def = {
.d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK
= SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
.d_SOC_LF_TIMER_STATUS0_ADDRESS = SOC_LF_TIMER_STATUS0_ADDRESS,
.d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK,
.d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB,
.d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS,