msm: camera: csiphy: Update logic for lane enablement
Currently lane enablement is happening as a part of lanemask field, which is send by UMD. Lane enablement should be purely depends on laneCnt and laneAssign attributes. Also, combo mode sensors needs to come with combo mode flag set from the UMD. This change updates the logic for lane enablement with respect to laneAssign and laneCnt, and also covers all combomode selection as per the request. This change also enables the sensors to acquire and streamon/streamoff at anytime in session. CRs-Fixed: 2677450 Change-Id: I4f0d3ffd7245a931c273611c9c4b7e503c038664 Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Dieser Commit ist enthalten in:
Jigarkumar Zala
Datei-Diff unterdrückt, da er zu groß ist
Diff laden
@@ -131,6 +131,7 @@ static int cam_csiphy_component_bind(struct device *dev,
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struct csiphy_device *new_csiphy_dev;
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int32_t rc = 0;
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struct platform_device *pdev = to_platform_device(dev);
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int i;
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new_csiphy_dev = devm_kzalloc(&pdev->dev,
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sizeof(struct csiphy_device), GFP_KERNEL);
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@@ -183,18 +184,23 @@ static int cam_csiphy_component_bind(struct device *dev,
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platform_set_drvdata(pdev, &(new_csiphy_dev->v4l2_dev_str.sd));
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new_csiphy_dev->bridge_intf.device_hdl[0] = -1;
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new_csiphy_dev->bridge_intf.device_hdl[1] = -1;
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new_csiphy_dev->bridge_intf.ops.get_dev_info =
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NULL;
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new_csiphy_dev->bridge_intf.ops.link_setup =
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NULL;
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new_csiphy_dev->bridge_intf.ops.apply_req =
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NULL;
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for (i = 0; i < CSIPHY_MAX_INSTANCES_PER_PHY; i++) {
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new_csiphy_dev->csiphy_info[i].hdl_data.device_hdl = -1;
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new_csiphy_dev->csiphy_info[i].hdl_data.session_hdl = -1;
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new_csiphy_dev->csiphy_info[i].csiphy_3phase = -1;
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new_csiphy_dev->csiphy_info[i].data_rate = 0;
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new_csiphy_dev->csiphy_info[i].settle_time = 0;
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new_csiphy_dev->csiphy_info[i].lane_cnt = 0;
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new_csiphy_dev->csiphy_info[i].lane_assign = 0;
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new_csiphy_dev->csiphy_info[i].lane_enable = 0;
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}
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new_csiphy_dev->ops.get_dev_info = NULL;
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new_csiphy_dev->ops.link_setup = NULL;
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new_csiphy_dev->ops.apply_req = NULL;
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new_csiphy_dev->acquire_count = 0;
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new_csiphy_dev->start_dev_count = 0;
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new_csiphy_dev->is_acquired_dev_combo_mode = 0;
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cpas_parms.cam_cpas_client_cb = NULL;
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cpas_parms.cell_index = new_csiphy_dev->soc_info.index;
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@@ -29,7 +29,7 @@
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#include "cam_context.h"
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#define MAX_CSIPHY 6
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#define MAX_DPHY_DATA_LN 4
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#define MAX_LRME_V4l2_EVENTS 30
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#define CSIPHY_NUM_CLK_MAX 16
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#define MAX_CSIPHY_REG_ARRAY 70
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@@ -41,6 +41,7 @@
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#define MAX_DATA_RATE_REGS 30
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#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
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#define CAM_CSIPHY_RX_CLK_SRC "cphy_rx_src_clk"
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#define CSIPHY_POWER_UP 0
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#define CSIPHY_POWER_DOWN 1
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@@ -53,20 +54,25 @@
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#define CSIPHY_2PH_REGS 5
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#define CSIPHY_3PH_REGS 6
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#define CSIPHY_MAX_INSTANCES 2
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#define CSIPHY_MAX_INSTANCES_PER_PHY 3
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#define CAM_CSIPHY_MAX_DPHY_LANES 4
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#define CAM_CSIPHY_MAX_CPHY_LANES 3
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#define CAM_CSIPHY_MAX_CPHY_DPHY_COMBO_LN 3
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#define CAM_CSIPHY_MAX_CPHY_COMBO_LN 3
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#define DPHY_LANE_0 BIT(0)
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#define CPHY_LANE_0 BIT(1)
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#define DPHY_LANE_1 BIT(2)
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#define CPHY_LANE_1 BIT(3)
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#define DPHY_LANE_2 BIT(4)
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#define CPHY_LANE_2 BIT(5)
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#define DPHY_LANE_3 BIT(6)
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#define DPHY_CLK_LN BIT(7)
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#define ENABLE_IRQ false
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#undef CDBG
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#ifdef CAM_CSIPHY_CORE_DEBUG
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#define CDBG(fmt, args...) pr_err(fmt, ##args)
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#else
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#define CDBG(fmt, args...) pr_debug(fmt, ##args)
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#endif
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enum cam_csiphy_state {
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CAM_CSIPHY_INIT,
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CAM_CSIPHY_ACQUIRE,
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@@ -111,6 +117,7 @@ struct csiphy_reg_parms_t {
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uint32_t csiphy_reset_array_size;
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uint32_t csiphy_2ph_config_array_size;
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uint32_t csiphy_3ph_config_array_size;
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uint32_t csiphy_2ph_3ph_config_array_size;
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uint32_t csiphy_cpas_cp_bits_per_phy;
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uint32_t csiphy_cpas_cp_is_interleaved;
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uint32_t csiphy_cpas_cp_2ph_offset;
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@@ -123,22 +130,17 @@ struct csiphy_reg_parms_t {
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* struct csiphy_intf_params
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* @device_hdl: Device Handle
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* @session_hdl: Session Handle
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* @ops: KMD operations
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* @crm_cb: Callback API pointers
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*/
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struct csiphy_intf_params {
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int32_t device_hdl[CSIPHY_MAX_INSTANCES];
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int32_t session_hdl[CSIPHY_MAX_INSTANCES];
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int32_t link_hdl[CSIPHY_MAX_INSTANCES];
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struct cam_req_mgr_kmd_ops ops;
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struct cam_req_mgr_crm_cb *crm_cb;
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struct csiphy_hdl_tbl {
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int32_t device_hdl;
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int32_t session_hdl;
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};
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/**
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* struct csiphy_reg_t
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* @reg_addr: Register address
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* @reg_data: Register data
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* @delay: Delay in us
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* @reg_addr: Register address
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* @reg_data: Register data
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* @delay: Delay in us
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* @csiphy_param_type: CSIPhy parameter type
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*/
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struct csiphy_reg_t {
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@@ -200,38 +202,35 @@ struct csiphy_ctrl_t {
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struct csiphy_reg_t (*csiphy_2ph_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_3ph_combo_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];
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enum cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev);
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enum cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev,
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int32_t index);
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struct data_rate_settings_t *data_rates_settings_table;
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};
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/**
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* cam_csiphy_param: Provides cmdbuffer structre
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* @lane_mask : Lane mask details
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* @lane_assign : Lane sensor will be using
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* @csiphy_3phase : Mentions DPHY or CPHY
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* @combo_mode : Info regarding combo_mode is enable / disable
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* @lane_cnt : Total number of lanes
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* @reserved
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* @3phase : Details whether 3Phase / 2Phase operation
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* @settle_time : Settling time in ms
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* @settle_time_combo_sensor : Settling time in ms
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* @data_rate : Data rate in mbps
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* @data_rate_combo_sensor: data rate of combo sensor
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* in the the same phy
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*
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* cam_csiphy_param : Provides cmdbuffer structure
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* @lane_assign : Lane sensor will be using
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* @lane_cnt : Total number of lanes
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* @secure_mode : To identify whether stream is secure/nonsecure
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* @lane_enable : Data Lane selection
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* @settle_time : Settling time in ms
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* @data_rate : Data rate in mbps
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* @csiphy_3phase : To identify DPHY or CPHY
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* @csiphy_cpas_cp_reg_mask : CP reg mask for phy instance
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* @hdl_data : CSIPHY handle table
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*/
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struct cam_csiphy_param {
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uint16_t lane_mask;
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uint16_t lane_assign;
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uint8_t csiphy_3phase;
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uint8_t combo_mode;
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uint8_t lane_cnt;
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uint8_t secure_mode[CSIPHY_MAX_INSTANCES];
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uint64_t settle_time;
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uint64_t settle_time_combo_sensor;
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uint64_t data_rate;
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uint64_t data_rate_combo_sensor;
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uint16_t lane_assign;
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uint8_t lane_cnt;
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uint8_t secure_mode;
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uint32_t lane_enable;
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uint64_t settle_time;
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uint64_t data_rate;
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int csiphy_3phase;
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uint64_t csiphy_cpas_cp_reg_mask;
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struct csiphy_hdl_tbl hdl_data;
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};
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/**
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@@ -255,41 +254,50 @@ struct cam_csiphy_param {
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* @csi_3phase: Is it a 3Phase mode
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* @ref_count: Reference count
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* @clk_lane: Clock lane
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* @rx_clk_src_idx: Phy src clk index
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* @acquire_count: Acquire device count
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* @start_dev_count: Start count
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* @is_acquired_dev_combo_mode: Flag that mentions whether already acquired
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* device is for combo mode
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* @soc_info: SOC information
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* @cpas_handle: CPAS handle
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* @config_count: Config reg count
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* @csiphy_cpas_cp_reg_mask: CP reg mask for phy instance
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* @current_data_rate: Data rate in mbps
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* @csiphy_3phase: To identify DPHY or CPHY at top level
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* @combo_mode: Info regarding combo_mode is enable / disable
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* @ops: KMD operations
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* @crm_cb: Callback API pointers
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*/
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struct csiphy_device {
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char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
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struct mutex mutex;
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uint32_t hw_version;
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enum cam_csiphy_state csiphy_state;
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struct csiphy_ctrl_t *ctrl_reg;
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uint32_t csiphy_max_clk;
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struct msm_cam_clk_info csiphy_3p_clk_info[2];
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struct clk *csiphy_3p_clk[2];
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unsigned char csi_3phase;
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int32_t ref_count;
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uint16_t lane_mask[MAX_CSIPHY];
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uint8_t is_csiphy_3phase_hw;
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uint8_t is_divisor_32_comp;
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uint8_t num_irq_registers;
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struct cam_subdev v4l2_dev_str;
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struct cam_csiphy_param csiphy_info;
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struct csiphy_intf_params bridge_intf;
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uint32_t clk_lane;
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uint32_t acquire_count;
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uint32_t start_dev_count;
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uint32_t is_acquired_dev_combo_mode;
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struct cam_hw_soc_info soc_info;
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uint32_t cpas_handle;
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uint32_t config_count;
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uint64_t csiphy_cpas_cp_reg_mask[CSIPHY_MAX_INSTANCES];
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char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
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struct mutex mutex;
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uint32_t hw_version;
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enum cam_csiphy_state csiphy_state;
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struct csiphy_ctrl_t *ctrl_reg;
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uint32_t csiphy_max_clk;
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struct msm_cam_clk_info csiphy_3p_clk_info[2];
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struct clk *csiphy_3p_clk[2];
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int32_t ref_count;
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uint16_t lane_mask[MAX_CSIPHY];
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uint8_t is_csiphy_3phase_hw;
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uint8_t is_divisor_32_comp;
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uint8_t num_irq_registers;
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struct cam_subdev v4l2_dev_str;
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struct cam_csiphy_param csiphy_info[
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CSIPHY_MAX_INSTANCES_PER_PHY];
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uint32_t clk_lane;
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uint8_t rx_clk_src_idx;
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uint32_t acquire_count;
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uint32_t start_dev_count;
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struct cam_hw_soc_info soc_info;
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uint32_t cpas_handle;
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uint32_t config_count;
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uint64_t current_data_rate;
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uint64_t csiphy_cpas_cp_reg_mask[
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CSIPHY_MAX_INSTANCES_PER_PHY];
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uint8_t session_max_device_support;
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uint8_t combo_mode;
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uint8_t cphy_dphy_combo_mode;
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struct cam_req_mgr_kmd_ops ops;
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struct cam_req_mgr_crm_cb *crm_cb;
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};
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/**
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@@ -126,26 +126,25 @@ int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev)
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enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev)
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enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev,
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int32_t index)
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{
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CAM_DBG(CAM_CSIPHY, "voting for SVS");
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return CAM_SVS_VOTE;
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}
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enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)
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enum cam_vote_level get_clk_voting_dynamic(
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struct csiphy_device *csiphy_dev, int32_t index)
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{
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uint32_t cam_vote_level = 0;
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uint32_t last_valid_vote = 0;
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struct cam_hw_soc_info *soc_info;
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uint64_t phy_data_rate = csiphy_dev->csiphy_info.data_rate;
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uint64_t phy_data_rate = csiphy_dev->csiphy_info[index].data_rate;
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soc_info = &csiphy_dev->soc_info;
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phy_data_rate = max(phy_data_rate, csiphy_dev->current_data_rate);
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if (csiphy_dev->is_acquired_dev_combo_mode)
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phy_data_rate = max(phy_data_rate,
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csiphy_dev->csiphy_info.data_rate_combo_sensor);
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if (csiphy_dev->csiphy_info.csiphy_3phase) {
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if (csiphy_dev->csiphy_info[index].csiphy_3phase) {
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if (csiphy_dev->is_divisor_32_comp)
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do_div(phy_data_rate, CSIPHY_DIVISOR_32);
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else
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@@ -156,19 +155,21 @@ enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)
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/* round off to next integer */
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phy_data_rate += 1;
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csiphy_dev->current_data_rate = phy_data_rate;
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for (cam_vote_level = 0;
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cam_vote_level < CAM_MAX_VOTE; cam_vote_level++) {
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if (soc_info->clk_level_valid[cam_vote_level] != true)
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continue;
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if (soc_info->clk_rate[cam_vote_level][0] >
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phy_data_rate) {
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if (soc_info->clk_rate[cam_vote_level]
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[csiphy_dev->rx_clk_src_idx] > phy_data_rate) {
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CAM_DBG(CAM_CSIPHY,
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"match detected %s : %llu:%d level : %d",
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soc_info->clk_name[0],
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soc_info->clk_name[csiphy_dev->rx_clk_src_idx],
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phy_data_rate,
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soc_info->clk_rate[cam_vote_level][0],
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soc_info->clk_rate[cam_vote_level]
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[csiphy_dev->rx_clk_src_idx],
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cam_vote_level);
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return cam_vote_level;
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}
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@@ -177,7 +178,7 @@ enum cam_vote_level get_clk_voting_dynamic(struct csiphy_device *csiphy_dev)
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return last_valid_vote;
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}
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int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev)
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int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index)
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{
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int32_t rc = 0;
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struct cam_hw_soc_info *soc_info;
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@@ -191,7 +192,7 @@ int32_t cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev)
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return rc;
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}
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vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev);
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vote_level = csiphy_dev->ctrl_reg->getclockvoting(csiphy_dev, index);
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rc = cam_soc_util_enable_platform_resource(soc_info, true,
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vote_level, ENABLE_IRQ);
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if (rc < 0) {
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@@ -466,6 +467,10 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
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csiphy_dev->csiphy_3p_clk[1] =
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soc_info->clk[i];
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continue;
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} else if (!strcmp(soc_info->clk_name[i],
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CAM_CSIPHY_RX_CLK_SRC)) {
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csiphy_dev->rx_clk_src_idx = i;
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continue;
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}
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CAM_DBG(CAM_CSIPHY, "clk_rate[%d] = %d", clk_cnt,
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@@ -21,9 +21,6 @@
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#include "cam_csiphy_dev.h"
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#include "cam_csiphy_core.h"
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#undef CDBG
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#define CDBG(fmt, args...) pr_debug(fmt, ##args)
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#define CSI_3PHASE_HW 1
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#define CSIPHY_VERSION_V35 0x35
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#define CSIPHY_VERSION_V10 0x10
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@@ -55,7 +52,7 @@ int cam_csiphy_parse_dt_info(struct platform_device *pdev,
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*
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* This API enables SOC related parameters
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*/
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int cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev);
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int cam_csiphy_enable_hw(struct csiphy_device *csiphy_dev, int32_t index);
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/**
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* @csiphy_dev: CSIPhy device structure
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|
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@@ -16,6 +16,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
|
||||
.csiphy_reset_array_size = 5,
|
||||
.csiphy_2ph_config_array_size = 16,
|
||||
.csiphy_3ph_config_array_size = 28,
|
||||
.csiphy_2ph_3ph_config_array_size = 0,
|
||||
.csiphy_2ph_clock_lane = 0x1,
|
||||
.csiphy_2ph_combo_ck_ln = 0x10,
|
||||
};
|
||||
|
||||
@@ -77,11 +77,12 @@ int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev,
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (offset >= CSIPHY_MAX_INSTANCES) {
|
||||
if (offset >= CSIPHY_MAX_INSTANCES_PER_PHY) {
|
||||
CAM_ERR(CAM_CSIPHY, "Invalid CSIPHY offset");
|
||||
rc = -EINVAL;
|
||||
} else if (qcom_scm_camera_protect_phy_lanes(protect,
|
||||
csiphy_dev->csiphy_cpas_cp_reg_mask[offset])) {
|
||||
csiphy_dev->csiphy_info[offset]
|
||||
.csiphy_cpas_cp_reg_mask)) {
|
||||
CAM_ERR(CAM_CSIPHY, "SCM call to hypervisor failed");
|
||||
rc = -EINVAL;
|
||||
}
|
||||
@@ -158,10 +159,11 @@ int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev,
|
||||
struct scm_desc description = {
|
||||
.arginfo = SCM_ARGS(2, SCM_VAL, SCM_VAL),
|
||||
.args[0] = protect,
|
||||
.args[1] = csiphy_dev->csiphy_cpas_cp_reg_mask[offset],
|
||||
.args[1] = csiphy_dev->csiphy_info[offset]
|
||||
.csiphy_cpas_cp_reg_mask,
|
||||
};
|
||||
|
||||
if (offset >= CSIPHY_MAX_INSTANCES) {
|
||||
if (offset >= CSIPHY_MAX_INSTANCES_PER_PHY) {
|
||||
CAM_ERR(CAM_CSIPHY, "Invalid CSIPHY offset");
|
||||
rc = -EINVAL;
|
||||
} else if (scm_call2(SCM_SIP_FNID(0x18, 0x7), &description)) {
|
||||
|
||||
@@ -324,23 +324,18 @@ struct cam_cmd_unconditional_wait {
|
||||
} __attribute__((packed));
|
||||
|
||||
/**
|
||||
* cam_csiphy_info: Provides cmdbuffer structre
|
||||
* @lane_mask : Lane mask details
|
||||
* @lane_assign : Lane sensor will be using
|
||||
* @csiphy_3phase : Total number of lanes
|
||||
* @combo_mode : Info regarding combo_mode is enable / disable
|
||||
* @lane_cnt : Total number of lanes
|
||||
* @secure_mode : Secure mode flag to enable / disable
|
||||
* @3phase : Details whether 3Phase / 2Phase operation
|
||||
* @settle_time : Settling time in ms
|
||||
* @data_rate : Data rate
|
||||
* cam_csiphy_info : Provides cmdbuffer structre
|
||||
* @lane_assign : Lane sensor will be using
|
||||
* @lane_cnt : Total number of lanes
|
||||
* @secure_mode : Secure mode flag to enable / disable
|
||||
* @settle_time : Settling time in ms
|
||||
* @data_rate : Data rate
|
||||
*
|
||||
*/
|
||||
struct cam_csiphy_info {
|
||||
__u16 lane_mask;
|
||||
__u16 reserved;
|
||||
__u16 lane_assign;
|
||||
__u8 csiphy_3phase;
|
||||
__u8 combo_mode;
|
||||
__u16 reserved1;
|
||||
__u8 lane_cnt;
|
||||
__u8 secure_mode;
|
||||
__u64 settle_time;
|
||||
@@ -349,14 +344,18 @@ struct cam_csiphy_info {
|
||||
|
||||
/**
|
||||
* cam_csiphy_acquire_dev_info : Information needed for
|
||||
* csiphy at the time of acquire
|
||||
* @combo_mode : Indicates the device mode of operation
|
||||
* @reserved
|
||||
* csiphy at the time of acquire
|
||||
* @combo_mode : Indicates the device mode of operation
|
||||
* @cphy_dphy_combo_mode : Info regarding cphy_dphy_combo mode
|
||||
* @csiphy_3phase : Details whether 3Phase / 2Phase operation
|
||||
* @reserve
|
||||
*
|
||||
*/
|
||||
struct cam_csiphy_acquire_dev_info {
|
||||
__u32 combo_mode;
|
||||
__u32 reserved;
|
||||
__u16 cphy_dphy_combo_mode;
|
||||
__u8 csiphy_3phase;
|
||||
__u8 reserve;
|
||||
} __attribute__((packed));
|
||||
|
||||
/**
|
||||
|
||||
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