disp: msm: sde: program misr at encoder kickoff stage

As per current design misr enable sequence is happening at
atomic check level. At this state, misr configuration may reset
if clocks are enabled through atomic commit sequence. This change
moves misr enable/disable sequence from debugfs context to
encoder kickoff to avoid misr register reset with idle pc.

Change-Id: Ia4faa200f96b76ba8c7ef3f45a26108e34b5e687
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>

msm/sde/sde_crtc.c

@@ -5864,7 +5864,6 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
 {
 	struct drm_crtc *crtc;
 	struct sde_crtc *sde_crtc;
-	int rc;
 	char buf[MISR_BUFF_SIZE + 1];
 	u32 frame_count, enable;
 	size_t buff_copy;
@@ -5899,14 +5898,9 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
 		return -EINVAL;
 	}
 
-	rc = pm_runtime_get_sync(crtc->dev->dev);
-	if (rc < 0)
-		return rc;
-
 	sde_crtc->misr_enable_debugfs = enable;
+	sde_crtc->misr_frame_count = frame_count;
 	sde_crtc->misr_reconfigure = true;
-	sde_crtc_misr_setup(crtc, enable, frame_count);
-	pm_runtime_put_sync(crtc->dev->dev);
 
 	return count;
 }

msm/sde/sde_encoder.c

@@ -4311,7 +4311,6 @@ static ssize_t _sde_encoder_misr_setup(struct file *file,
 		const char __user *user_buf, size_t count, loff_t *ppos)
 {
 	struct sde_encoder_virt *sde_enc;
-	int rc;
 	char buf[MISR_BUFF_SIZE + 1];
 	size_t buff_copy;
 	u32 frame_count, enable;
@@ -4345,15 +4344,9 @@ static ssize_t _sde_encoder_misr_setup(struct file *file,
 	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
 		return -EINVAL;
 
-	rc = pm_runtime_get_sync(drm_enc->dev->dev);
-	if (rc < 0)
-		return rc;
-
 	sde_enc->misr_enable = enable;
 	sde_enc->misr_reconfigure = true;
 	sde_enc->misr_frame_count = frame_count;
-	sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
-	pm_runtime_put_sync(drm_enc->dev->dev);
 	return count;
 }