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disp: msm: sde: program misr at encoder kickoff stage

Selaa lähdekoodia 
As per current design misr enable sequence is happening at
atomic check level. At this state, misr configuration may reset
if clocks are enabled through atomic commit sequence. This change
moves misr enable/disable sequence from debugfs context to
encoder kickoff to avoid misr register reset with idle pc.

Change-Id: Ia4faa200f96b76ba8c7ef3f45a26108e34b5e687
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This commit is contained in:
Narendra Muppalla
2020-07-27 15:36:27 -07:00
committed by Gerrit - the friendly Code Review server
vanhempi 32e305e278
commit f8e7d9d5d1
2 muutettua tiedostoa jossa 1 lisäystä ja 14 poistoa
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7
msm/sde/sde_encoder.c
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@@ -4311,7 +4311,6 @@ static ssize_t _sde_encoder_misr_setup(struct file *file,
const char __user *user_buf, size_t count, loff_t *ppos)
{
struct sde_encoder_virt *sde_enc;
int rc;
char buf[MISR_BUFF_SIZE + 1];
size_t buff_copy;
u32 frame_count, enable;
@@ -4345,15 +4344,9 @@ static ssize_t _sde_encoder_misr_setup(struct file *file,
if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
return -EINVAL;
rc = pm_runtime_get_sync(drm_enc->dev->dev);
if (rc < 0)
return rc;
sde_enc->misr_enable = enable;
sde_enc->misr_reconfigure = true;
sde_enc->misr_frame_count = frame_count;
sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
pm_runtime_put_sync(drm_enc->dev->dev);
return count;
}