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disp: msm: sde: program misr at encoder kickoff stage

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As per current design misr enable sequence is happening at
atomic check level. At this state, misr configuration may reset
if clocks are enabled through atomic commit sequence. This change
moves misr enable/disable sequence from debugfs context to
encoder kickoff to avoid misr register reset with idle pc.

Change-Id: Ia4faa200f96b76ba8c7ef3f45a26108e34b5e687
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This commit is contained in:
Narendra Muppalla
2020-07-27 15:36:27 -07:00
committed by Gerrit - the friendly Code Review server
parent 32e305e278
commit f8e7d9d5d1
2 changed files with 1 additions and 14 deletions
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8
msm/sde/sde_crtc.c
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@@ -5864,7 +5864,6 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
{
struct drm_crtc *crtc;
struct sde_crtc *sde_crtc;
int rc;
char buf[MISR_BUFF_SIZE + 1];
u32 frame_count, enable;
size_t buff_copy;
@@ -5899,14 +5898,9 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
return -EINVAL;
}
rc = pm_runtime_get_sync(crtc->dev->dev);
if (rc < 0)
return rc;
sde_crtc->misr_enable_debugfs = enable;
sde_crtc->misr_frame_count = frame_count;
sde_crtc->misr_reconfigure = true;
sde_crtc_misr_setup(crtc, enable, frame_count);
pm_runtime_put_sync(crtc->dev->dev);
return count;
}