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disp: msm: sde: enable 32bit intf te registers

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This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.

Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This commit is contained in:
Nilaan Gunabalachandran
2022-05-13 11:00:29 -04:00
committed by Gerrit - the friendly Code Review server
parent 00369e3266
commit f73f15ae39
5 changed files with 81 additions and 25 deletions
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6
msm/sde/sde_hw_intf.h
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@@ -56,8 +56,10 @@ struct intf_status {
};
struct intf_tear_status {
u32 read_count; /* frame & line count for tear init value */
u32 write_count; /* frame & line count for tear write */
u32 read_frame_count; /* frame count for tear init value */
u32 read_line_count; /* line count for tear init value */
u32 write_frame_count; /* frame count for tear write */
u32 write_line_count; /* line count for tear write */
};
struct intf_avr_params {