diff --git a/icnss2/main.c b/icnss2/main.c index 2e2910e8f7..902b81d0de 100644 --- a/icnss2/main.c +++ b/icnss2/main.c @@ -3400,6 +3400,8 @@ int icnss_get_soc_info(struct device *dev, struct icnss_soc_info *info) info->rd_card_chain_cap = priv->rd_card_chain_cap; info->phy_he_channel_width_cap = priv->phy_he_channel_width_cap; info->phy_qam_cap = priv->phy_qam_cap; + memcpy(&info->dev_mem_info, &priv->dev_mem_info, + sizeof(info->dev_mem_info)); return 0; } diff --git a/icnss2/main.h b/icnss2/main.h index 71ab78c5b0..94c22c5e9b 100644 --- a/icnss2/main.h +++ b/icnss2/main.h @@ -433,6 +433,7 @@ struct icnss_priv { uint32_t nr_mem_region; struct icnss_mem_region_info mem_region[WLFW_MAX_NUM_MEMORY_REGIONS]; + struct icnss_dev_mem_info dev_mem_info[ICNSS_MAX_DEV_MEM_NUM]; struct dentry *root_dentry; spinlock_t on_off_lock; struct icnss_stats stats; diff --git a/icnss2/qmi.c b/icnss2/qmi.c index 2d66444316..fbde170cae 100644 --- a/icnss2/qmi.c +++ b/icnss2/qmi.c @@ -695,7 +695,7 @@ out: int wlfw_cap_send_sync_msg(struct icnss_priv *priv) { - int ret; + int ret = 0, i = 0; struct wlfw_cap_req_msg_v01 *req; struct wlfw_cap_resp_msg_v01 *resp; struct qmi_txn txn; @@ -774,6 +774,18 @@ int wlfw_cap_send_sync_msg(struct icnss_priv *priv) WLFW_MAX_TIMESTAMP_LEN + 1); } + if (resp->dev_mem_info_valid) { + for (i = 0; i < QMI_WLFW_MAX_DEV_MEM_NUM_V01; i++) { + priv->dev_mem_info[i].start = + resp->dev_mem_info[i].start; + priv->dev_mem_info[i].size = + resp->dev_mem_info[i].size; + icnss_pr_info("Device memory info[%d]: start = 0x%llx, size = 0x%llx\n", + i, priv->dev_mem_info[i].start, + priv->dev_mem_info[i].size); + } + } + if (resp->voltage_mv_valid) { priv->cpr_info.voltage = resp->voltage_mv; icnss_pr_dbg("Voltage for CPR: %dmV\n", diff --git a/inc/icnss2.h b/inc/icnss2.h index deb8b582a6..e744cba692 100644 --- a/inc/icnss2.h +++ b/inc/icnss2.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ICNSS_WLAN_H_ #define _ICNSS_WLAN_H_ @@ -13,6 +13,7 @@ #define IWCN_MAX_IRQ_REGISTRATIONS 32 #define ICNSS_MAX_TIMESTAMP_LEN 32 #define ICNSS_WLFW_MAX_BUILD_ID_LEN 128 +#define ICNSS_MAX_DEV_MEM_NUM 4 #define DEVICE_NAME_MAX 10 enum icnss_uevent { @@ -40,6 +41,11 @@ struct icnss_uevent_data { void *data; }; +struct icnss_dev_mem_info { + u64 start; + u64 size; +}; + /* Device information like supported device ids, etc*/ struct device_info { char name[DEVICE_NAME_MAX]; @@ -165,6 +171,7 @@ struct icnss_soc_info { enum icnss_rd_card_chain_cap rd_card_chain_cap; enum icnss_phy_he_channel_width_cap phy_he_channel_width_cap; enum icnss_phy_qam_cap phy_qam_cap; + struct icnss_dev_mem_info dev_mem_info[ICNSS_MAX_DEV_MEM_NUM]; }; #define icnss_register_driver(ops) \