qcacmn: Refine HW cookie conversion

(1)naming change in HW CC related function
(2)refinement for cookie ID generation regardless of
SPT page address 4k aligned or not
(3)move CMEM size check under cookie conversion macro

Change-Id: Ib32d802f5512e5facfa4130826406943fb3d27f1
CRs-Fixed: 2977304

dp/wifi3.0/be/dp_be.c

@@ -39,14 +39,69 @@ qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
 	}
 }
 
-static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
+#ifdef DP_FEATURE_HW_COOKIE_CONVERSION
+/**
+ * dp_cc_reg_cfg_init() - initialize and configure HW cookie
+			  conversion register
+ * @soc: SOC handle
+ * @cc_ctx: cookie conversion context pointer
+ * @is_4k_align: page address 4k alignd
+ *
+ * Return: None
+ */
+static void dp_cc_reg_cfg_init(struct dp_soc *soc,
+			       struct dp_hw_cookie_conversion_t *cc_ctx,
+			       bool is_4k_align)
 {
-	struct dp_soc *soc = &be_soc->soc;
-	struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
-	uint32_t max_tx_rx_desc_num, num_spt_pages, i = 0;
-	struct dp_spt_page_desc *page_desc_elem;
-	struct qdf_mem_dma_page_t *dma_page;
+	struct hal_hw_cc_config cc_cfg = { 0 };
+
+	cc_cfg.lut_base_addr_31_0 = cc_ctx->cmem_base;
+	cc_cfg.cc_global_en = soc->wlan_cfg_ctx->hw_cc_enabled;
+	cc_cfg.page_4k_align = is_4k_align;
+	cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
+	cc_cfg.cookie_page_msb = DP_CC_DESC_ID_PPT_PAGE_OS_MSB;
+	/* 36th bit should be 1 then HW know this is CMEM address */
+	cc_cfg.lut_base_addr_39_32 = 0x10;
+
+	cc_cfg.wbm2sw6_cc_en = 1;
+	cc_cfg.wbm2sw5_cc_en = 1;
+	cc_cfg.wbm2sw4_cc_en = 1;
+	cc_cfg.wbm2sw3_cc_en = 1;
+	cc_cfg.wbm2sw2_cc_en = 1;
+	cc_cfg.wbm2sw1_cc_en = 1;
+	cc_cfg.wbm2sw0_cc_en = 1;
+	cc_cfg.wbm2fw_cc_en = 0;
+
+	hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
+}
 
+/**
+ * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
+ * @hal_soc_hdl: HAL SOC handle
+ * @offset: CMEM address
+ * @value: value to write
+ *
+ * Return: None.
+ */
+static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
+				       uint32_t offset,
+				       uint32_t value)
+{
+	hal_cmem_write(hal_soc_hdl, offset, value);
+}
+
+/**
+ * dp_hw_cc_cmem_addr_init() - Check and initialize CMEM base address for
+			       HW cookie conversion
+ * @soc: SOC handle
+ * @cc_ctx: cookie conversion context pointer
+ *
+ * Return: 0 in case of success, else error value
+ */
+static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
+				struct dp_soc *soc,
+				struct dp_hw_cookie_conversion_t *cc_ctx)
+{
 	/* get CMEM for cookie conversion */
 	if (soc->cmem_size < DP_CC_PPT_MEM_SIZE) {
 		dp_err("cmem_size %llu bytes < 4K", soc->cmem_size);
@@ -55,6 +110,41 @@ static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
 	cc_ctx->cmem_base = (uint32_t)(soc->cmem_base +
 					DP_CC_MEM_OFFSET_IN_CMEM);
 
+	return QDF_STATUS_SUCCESS;
+}
+
+#else
+
+static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
+				      struct dp_hw_cookie_conversion_t *cc_ctx,
+				      bool is_4k_align) {}
+
+static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
+				       uint32_t offset,
+				       uint32_t value)
+{ }
+
+static inline QDF_STATUS dp_hw_cc_cmem_addr_init(
+				struct dp_soc *soc,
+				struct dp_hw_cookie_conversion_t *cc_ctx)
+{
+	return QDF_STATUS_SUCCESS;
+}
+#endif
+
+static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
+{
+	struct dp_soc *soc = &be_soc->soc;
+	struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
+	uint32_t max_tx_rx_desc_num, num_spt_pages, i = 0;
+	struct dp_spt_page_desc *spt_desc;
+	struct qdf_mem_dma_page_t *dma_page;
+	QDF_STATUS qdf_status;
+
+	qdf_status = dp_hw_cc_cmem_addr_init(soc, cc_ctx);
+	if (!QDF_IS_STATUS_SUCCESS(qdf_status))
+		return qdf_status;
+
 	/* estimate how many SPT DDR pages needed */
 	max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
 			WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
@@ -78,7 +168,7 @@ static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
 	}
 
 	/* initial page desc */
-	page_desc_elem = cc_ctx->page_desc_base;
+	spt_desc = cc_ctx->page_desc_base;
 	dma_page = cc_ctx->page_pool.dma_pages;
 	while (i < num_spt_pages) {
 		/* check if page address 4K aligned */
@@ -88,9 +178,9 @@ static QDF_STATUS dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc)
 			goto fail_1;
 		}
 
-		page_desc_elem[i].page_v_addr =
+		spt_desc[i].page_v_addr =
 					dma_page[i].page_v_addr_start;
-		page_desc_elem[i].page_p_addr =
+		spt_desc[i].page_p_addr =
 					dma_page[i].page_p_addr;
 		i++;
 	}
@@ -121,100 +211,34 @@ static QDF_STATUS dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc)
 	return QDF_STATUS_SUCCESS;
 }
 
-#ifdef DP_FEATURE_HW_COOKIE_CONVERSION
-/**
- * dp_cc_reg_cfg_init() - initialize and configure HW cookie
-			  conversion register
- * @soc: SOC handle
- * @cc_ctx: cookie conversion context pointer
- * @is_4k_align: page address 4k alignd
- *
- * Return: None
- */
-static void dp_cc_reg_cfg_init(struct dp_soc *soc,
-			       struct dp_hw_cookie_conversion_t *cc_ctx,
-			       bool is_4k_align)
-{
-	struct hal_hw_cc_config cc_cfg = { 0 };
-
-	cc_cfg.lut_base_addr_31_0 = cc_ctx->cmem_base;
-	cc_cfg.cc_global_en = soc->wlan_cfg_ctx->hw_cc_enabled;
-	cc_cfg.page_4k_align = is_4k_align;
-	cc_cfg.cookie_offset_msb = DP_CC_DESC_ID_SPT_VA_OS_MSB;
-	cc_cfg.cookie_page_msb = is_4k_align ?
-				DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MSB :
-				DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MSB;
-	/* 36th bit should be 1 then HW know this is CMEM address */
-	cc_cfg.lut_base_addr_39_32 = 0x10;
-
-	cc_cfg.wbm2sw6_cc_en = 1;
-	cc_cfg.wbm2sw5_cc_en = 1;
-	cc_cfg.wbm2sw4_cc_en = 1;
-	cc_cfg.wbm2sw3_cc_en = 1;
-	cc_cfg.wbm2sw2_cc_en = 1;
-	cc_cfg.wbm2sw1_cc_en = 1;
-	cc_cfg.wbm2sw0_cc_en = 1;
-	cc_cfg.wbm2fw_cc_en = 0;
-
-	hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
-}
-
-/**
- * dp_hw_cc_cmem_write() - DP wrapper function for CMEM buffer writing
- * @hal_soc_hdl: HAL SOC handle
- * @offset: CMEM address
- * @value: value to write
- *
- * Return: None.
- */
-static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
-				       uint32_t offset,
-				       uint32_t value)
-{
-	hal_cmem_write(hal_soc_hdl, offset, value);
-}
-
-#else
-
-static inline void dp_cc_reg_cfg_init(struct dp_soc *soc,
-				      struct dp_hw_cookie_conversion_t *cc_ctx,
-				      bool is_4k_align) {}
-
-static inline void dp_hw_cc_cmem_write(hal_soc_handle_t hal_soc_hdl,
-				       uint32_t offset,
-				       uint32_t value)
-{ }
-
-#endif
-
 static QDF_STATUS dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc)
 {
 	struct dp_soc *soc = &be_soc->soc;
 	struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
 	uint32_t i = 0;
-	struct dp_spt_page_desc *page_desc_elem;
+	struct dp_spt_page_desc *spt_desc;
 
 	if (!cc_ctx->total_page_num) {
 		dp_err("total page num is 0");
 		return QDF_STATUS_E_INVAL;
 	}
 
-	page_desc_elem = cc_ctx->page_desc_base;
+	spt_desc = cc_ctx->page_desc_base;
 	while (i < cc_ctx->total_page_num) {
 		/* write page PA to CMEM */
 		dp_hw_cc_cmem_write(soc->hal_soc,
 				    (cc_ctx->cmem_base +
 				     i * DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED),
-				    (page_desc_elem[i].page_p_addr >>
+				    (spt_desc[i].page_p_addr >>
 				     DP_CC_PPT_ENTRY_HW_APEND_BITS_4K_ALIGNED));
 
-		page_desc_elem[i].ppt_index = i;
-		page_desc_elem[i].avail_entry_index = 0;
+		spt_desc[i].ppt_index = i;
+		spt_desc[i].avail_entry_index = 0;
 		/* link page desc */
 		if ((i + 1) != cc_ctx->total_page_num)
-			page_desc_elem[i].next = &page_desc_elem[i + 1];
+			spt_desc[i].next = &spt_desc[i + 1];
 		else
-			page_desc_elem[i].next = NULL;
+			spt_desc[i].next = NULL;
 		i++;
 	}
 
@@ -240,13 +264,13 @@ static QDF_STATUS dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc)
 uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
 				   struct dp_spt_page_desc **list_head,
 				   struct dp_spt_page_desc **list_tail,
-				   uint16_t desc_num)
+				   uint16_t num_desc)
 {
 	uint16_t num_pages, count;
 	struct dp_hw_cookie_conversion_t *cc_ctx = &be_soc->hw_cc_ctx;
 
-	num_pages = (desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES) +
-			(desc_num % DP_CC_SPT_PAGE_MAX_ENTRIES ? 1 : 0);
+	num_pages = (num_desc / DP_CC_SPT_PAGE_MAX_ENTRIES) +
+			(num_desc % DP_CC_SPT_PAGE_MAX_ENTRIES ? 1 : 0);
 
 	if (num_pages > cc_ctx->free_page_num) {
 		dp_err("fail: num_pages required %d > free_page_num %d",

dp/wifi3.0/be/dp_be.h

@@ -46,30 +46,24 @@
 
 #define DP_CC_DESC_ID_SPT_VA_OS_MSB 8
 
-/* for 4k unaligned case */
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT 9
+/* higher 11 bits in Desc ID for offset in CMEM of PPT */
+#define DP_CC_DESC_ID_PPT_PAGE_OS_LSB 9
 
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MASK 0xFFE00
+#define DP_CC_DESC_ID_PPT_PAGE_OS_MSB 19
 
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_LSB 9
+#define DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT 9
 
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MSB 19
+#define DP_CC_DESC_ID_PPT_PAGE_OS_MASK 0xFFE00
 
+/*
+ * page 4K unaligned case, single SPT page physical address
+ * need 8 bytes in PPT
+ */
 #define DP_CC_PPT_ENTRY_SIZE_4K_UNALIGNED 8
-
-/* for 4k aligned case */
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT 10
-
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MASK 0xFFC00
-
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_LSB 10
-
-#define DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MSB 19
-
-#define DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT 9
-
-#define DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_MASK 0x200
-
+/*
+ * page 4K aligned case, single SPT page physical address
+ * need 4 bytes in PPT
+ */
 #define DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED 4
 
 /* 4K aligned case, number of bits HW append for one PPT entry value */
@@ -264,14 +258,14 @@ struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer)
  * @be_soc: beryllium soc handler
  * @list_head: pointer to page desc head
  * @list_tail: pointer to page desc tail
- * @desc_num: number of TX/RX Descs required for SPT pages
+ * @num_desc: number of TX/RX Descs required for SPT pages
  *
  * Return: number of SPT page Desc allocated
  */
 uint16_t dp_cc_spt_page_desc_alloc(struct dp_soc_be *be_soc,
 				   struct dp_spt_page_desc **list_head,
 				   struct dp_spt_page_desc **list_tail,
-				   uint16_t desc_num);
+				   uint16_t num_desc);
 /**
  * dp_cc_spt_page_desc_free() - free SPT DDR page descriptor to pool
  * @be_soc: beryllium soc handler
@@ -289,49 +283,35 @@ void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
 				DDR page 4K aligned or not
  * @ppt_index: offset index in primary page table
  * @spt_index: offset index in sceondary DDR page
- * @page_4k_align: DDR page address 4K aligned or not
  *
- * for 4K aligned DDR page, ppt_index offset is using 4 bytes entry,
- * while HW use 8 bytes offset index, need 10th bit to indicate it's
- * in high 32bits or low 32bits.
- * for 4k un-aligned DDR page, ppt_index offset is using 8bytes entry,
- * it's match with HW assuming.
+ * Generate SW cookie ID to match as HW expected
  *
  * Return: cookie ID
  */
 static inline uint32_t dp_cc_desc_id_generate(uint16_t ppt_index,
-					      uint16_t spt_index,
-					      bool page_4k_align)
+					      uint16_t spt_index)
 {
-	uint32_t id = 0;
-
-	if (qdf_likely(page_4k_align))
-		id =
-		((ppt_index / 2) <<
-		DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT) |
-		((ppt_index % 2) <<
-		DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT) |
-		spt_index;
-	else
-		id =
-		(ppt_index <<
-		DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT) |
-		spt_index;
-
-	return id;
+	/*
+	 * for 4k aligned case, cmem entry size is 4 bytes,
+	 * HW index from bit19~bit10 value = ppt_index / 2, high 32bits flag
+	 * from bit9 value = ppt_index % 2, then bit 19 ~ bit9 value is
+	 * exactly same with original ppt_index value.
+	 * for 4k un-aligned case, cmem entry size is 8 bytes.
+	 * bit19 ~ bit9 will be HW index value, same as ppt_index value.
+	 */
+	return ((((uint32_t)ppt_index) << DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT) |
+		spt_index);
 }
 
 /**
  * dp_cc_desc_va_find() - find TX/RX Descs virtual address by ID
  * @be_soc: be soc handle
  * @desc_id: TX/RX Dess ID
- * @page_4k_align: DDR page address 4K aligned or not
  *
  * Return: TX/RX Desc virtual address
  */
 static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
-					uint32_t desc_id,
-					bool page_4k_align)
+					uint32_t desc_id)
 {
 	struct dp_soc_be *be_soc;
 	struct dp_hw_cookie_conversion_t *cc_ctx;
@@ -340,19 +320,8 @@ static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
 
 	be_soc = dp_get_be_soc_from_dp_soc(soc);
 	cc_ctx = &be_soc->hw_cc_ctx;
-	if (qdf_likely(page_4k_align))
-		ppt_page_id =
-			(((desc_id &
-			DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_MASK) >>
-			DP_CC_DESC_ID_PPT_PAGE_OS_4K_ALIGNED_SHIFT) * 2) +
-			((desc_id &
-			DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_MASK) >>
-			DP_CC_DESC_ID_PPT_PAGE_HIGH_32BIT_4K_ALIGNED_SHIFT);
-	else
-		ppt_page_id =
-			(desc_id &
-			DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_MASK) >>
-			DP_CC_DESC_ID_PPT_PAGE_OS_4K_UNALIGNED_SHIFT;
+	ppt_page_id = (desc_id & DP_CC_DESC_ID_PPT_PAGE_OS_MASK) >>
+			DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT;
 
 	spt_va_id = (desc_id & DP_CC_DESC_ID_SPT_VA_OS_MASK) >>
 			DP_CC_DESC_ID_SPT_VA_OS_SHIFT;

dp/wifi3.0/be/dp_be_rx.c

@@ -820,8 +820,7 @@ dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
 
 		rx_desc_elem->rx_desc.cookie =
 			dp_cc_desc_id_generate(page_desc->ppt_index,
-					       page_desc->avail_entry_index,
-					       true);
+					       page_desc->avail_entry_index);
 		rx_desc_elem->rx_desc.pool_id = pool_id;
 		rx_desc_elem->rx_desc.in_use = 0;
 		rx_desc_elem = rx_desc_elem->next;
@@ -876,8 +875,7 @@ dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
 
 		rx_desc_pool->array[i].rx_desc.cookie =
 			dp_cc_desc_id_generate(page_desc->ppt_index,
-					       page_desc->avail_entry_index,
-					       true);
+					       page_desc->avail_entry_index);
 
 		rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
 		rx_desc_pool->array[i].rx_desc.in_use = 0;
@@ -963,7 +961,7 @@ QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
 		uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
 
 		*r_rx_desc = (struct dp_rx_desc *)
-				dp_cc_desc_find(soc, cookie, true);
+				dp_cc_desc_find(soc, cookie);
 	}
 
 	return QDF_STATUS_SUCCESS;
@@ -988,7 +986,7 @@ QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
 	uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
 
 	*r_rx_desc = (struct dp_rx_desc *)
-			dp_cc_desc_find(soc, cookie, true);
+			dp_cc_desc_find(soc, cookie);
 
 	return QDF_STATUS_SUCCESS;
 }
@@ -997,7 +995,7 @@ QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
 struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
 					     uint32_t cookie)
 {
-	return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie, true);
+	return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
 }
 
 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ

dp/wifi3.0/be/dp_be_rx.h

@@ -92,8 +92,7 @@ dp_rx_desc_sw_cc_check(struct dp_soc *soc,
 	if (qdf_unlikely(!(*r_rx_desc))) {
 		*r_rx_desc = (struct dp_rx_desc *)
 				dp_cc_desc_find(soc,
-						rx_buf_cookie,
-						true);
+						rx_buf_cookie);
 	}
 }
 #else

dp/wifi3.0/be/dp_be_tx.c

@@ -41,7 +41,7 @@ void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
 		/* SW do cookie conversion to VA */
 		tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
 		*r_tx_desc =
-		(struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id, true);
+		(struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
 	}
 }
 #else
@@ -64,7 +64,7 @@ void dp_tx_comp_get_params_from_hal_desc_be(struct dp_soc *soc,
 	/* SW do cookie conversion to VA */
 	tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
 	*r_tx_desc =
-	(struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id, true);
+	(struct dp_tx_desc_s *)dp_cc_desc_find(soc, tx_desc_id);
 }
 #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
 
@@ -379,16 +379,16 @@ void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
 }
 
 QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
-				   uint16_t pool_desc_num,
+				   uint16_t num_elem,
 				   uint8_t pool_id)
 {
 	struct dp_tx_desc_pool_s *tx_desc_pool;
 	struct dp_soc_be *be_soc;
 	struct dp_spt_page_desc *page_desc;
 	struct dp_spt_page_desc_list *page_desc_list;
-	struct dp_tx_desc_s *tx_desc_elem;
+	struct dp_tx_desc_s *tx_desc;
 
-	if (!pool_desc_num) {
+	if (!num_elem) {
 		dp_err("desc_num 0 !!");
 		return QDF_STATUS_E_FAILURE;
 	}
@@ -402,7 +402,7 @@ QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
 		dp_cc_spt_page_desc_alloc(be_soc,
 					  &page_desc_list->spt_page_list_head,
 					  &page_desc_list->spt_page_list_tail,
-					  pool_desc_num);
+					  num_elem);
 
 	if (!page_desc_list->num_spt_pages) {
 		dp_err("fail to allocate cookie conversion spt pages");
@@ -411,17 +411,16 @@ QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
 
 	/* put each TX Desc VA to SPT pages and get corresponding ID */
 	page_desc = page_desc_list->spt_page_list_head;
-	tx_desc_elem = tx_desc_pool->freelist;
-	while (tx_desc_elem) {
+	tx_desc = tx_desc_pool->freelist;
+	while (tx_desc) {
 		DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
 					 page_desc->avail_entry_index,
-					 tx_desc_elem);
-		tx_desc_elem->id =
+					 tx_desc);
+		tx_desc->id =
 			dp_cc_desc_id_generate(page_desc->ppt_index,
-					       page_desc->avail_entry_index,
-					       true);
-		tx_desc_elem->pool_id = pool_id;
-		tx_desc_elem = tx_desc_elem->next;
+					       page_desc->avail_entry_index);
+		tx_desc->pool_id = pool_id;
+		tx_desc = tx_desc->next;
 
 		page_desc->avail_entry_index++;
 		if (page_desc->avail_entry_index >=

dp/wifi3.0/be/dp_be_tx.h

@@ -113,13 +113,13 @@ void dp_tx_update_bank_profile(struct dp_soc_be *be_soc,
 /**
  * dp_tx_desc_pool_init_be() - Initialize Tx Descriptor pool(s)
  * @soc: Handle to DP Soc structure
- * @pool_desc_num: pool descriptor number
+ * @num_elem: number of descriptor in pool
  * @pool_id: pool ID to allocate
  *
  * Return: QDF_STATUS_SUCCESS - success, others - failure
  */
 QDF_STATUS dp_tx_desc_pool_init_be(struct dp_soc *soc,
-				   uint16_t pool_desc_num,
+				   uint16_t num_elem,
 				   uint8_t pool_id);
 /**
  * dp_tx_desc_pool_deinit_be() - De-initialize Tx Descriptor pool(s)

dp/wifi3.0/dp_types.h

@@ -412,6 +412,7 @@ enum dp_ctxt_type {
  * @DP_RX_DESC_BUF_TYPE: DP RX SW descriptor
  * @DP_RX_DESC_STATUS_TYPE: DP RX SW descriptor for monitor status
  * @DP_HW_LINK_DESC_TYPE: DP HW link descriptor
+ * @DP_HW_CC_SPT_PAGE_TYPE: DP pages for HW CC secondary page table
  */
 enum dp_desc_type {
 	DP_TX_DESC_TYPE,
@@ -422,9 +423,7 @@ enum dp_desc_type {
 	DP_RX_DESC_BUF_TYPE,
 	DP_RX_DESC_STATUS_TYPE,
 	DP_HW_LINK_DESC_TYPE,
-#ifdef CONFIG_BERYLLIUM
 	DP_HW_CC_SPT_PAGE_TYPE,
-#endif
 };
 
 /**
@@ -1586,7 +1585,7 @@ struct dp_arch_ops {
 				  uint8_t reo_ring_num, uint32_t quota);
 
 	QDF_STATUS (*dp_tx_desc_pool_init)(struct dp_soc *soc,
-					   uint16_t pool_desc_num,
+					   uint16_t num_elem,
 					   uint8_t pool_id);
 	void (*dp_tx_desc_pool_deinit)(
 				struct dp_soc *soc,

dp/wifi3.0/li/dp_li_tx.c

@@ -217,28 +217,28 @@ ring_access_fail:
 }
 
 QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
-				   uint16_t pool_desc_num,
+				   uint16_t num_elem,
 				   uint8_t pool_id)
 {
 	uint32_t id, count, page_id, offset, pool_id_32;
-	struct dp_tx_desc_s *tx_desc_elem;
+	struct dp_tx_desc_s *tx_desc;
 	struct dp_tx_desc_pool_s *tx_desc_pool;
 	uint16_t num_desc_per_page;
 
 	tx_desc_pool = &soc->tx_desc[pool_id];
-	tx_desc_elem = tx_desc_pool->freelist;
+	tx_desc = tx_desc_pool->freelist;
 	count = 0;
 	pool_id_32 = (uint32_t)pool_id;
 	num_desc_per_page = tx_desc_pool->desc_pages.num_element_per_page;
-	while (tx_desc_elem) {
+	while (tx_desc) {
 		page_id = count / num_desc_per_page;
 		offset = count % num_desc_per_page;
 		id = ((pool_id_32 << DP_TX_DESC_ID_POOL_OS) |
 			(page_id << DP_TX_DESC_ID_PAGE_OS) | offset);
 
-		tx_desc_elem->id = id;
-		tx_desc_elem->pool_id = pool_id;
-		tx_desc_elem = tx_desc_elem->next;
+		tx_desc->id = id;
+		tx_desc->pool_id = pool_id;
+		tx_desc = tx_desc->next;
 		count++;
 	}
 

dp/wifi3.0/li/dp_li_tx.h

@@ -56,13 +56,13 @@ void dp_tx_comp_get_params_from_hal_desc_li(struct dp_soc *soc,
 /**
  * dp_tx_desc_pool_init_li() - Initialize Tx Descriptor pool(s)
  * @soc: Handle to DP Soc structure
- * @pool_desc_num: pool descriptor number
+ * @num_elem: pool descriptor number
  * @pool_id: pool to allocate
  *
  * Return: QDF_STATUS_SUCCESS - success, others - failure
  */
 QDF_STATUS dp_tx_desc_pool_init_li(struct dp_soc *soc,
-				   uint16_t pool_desc_num,
+				   uint16_t num_elem,
 				   uint8_t pool_id);
 
 /**