From f518df07274823e9375434574e5f32a87f985943 Mon Sep 17 00:00:00 2001 From: Jeff Johnson Date: Wed, 8 Feb 2023 17:24:55 -0800 Subject: [PATCH] qcacmn: Fix hal/wifi3.0/be documentation The kernel-doc script identified some documentation issues in the hal/wifi3.0/be folder, so fix them. Change-Id: I9730c36e4d36dbe0ae551067c5c500441f07569f CRs-Fixed: 3400933 --- hal/wifi3.0/be/hal_be_api.h | 50 +-- hal/wifi3.0/be/hal_be_api_mon.h | 55 ++-- hal/wifi3.0/be/hal_be_generic_api.c | 53 +--- hal/wifi3.0/be/hal_be_generic_api.h | 72 ++--- hal/wifi3.0/be/hal_be_reo.c | 13 +- hal/wifi3.0/be/hal_be_reo.h | 6 +- hal/wifi3.0/be/hal_be_rx_tlv.h | 451 ++++++++++++++-------------- hal/wifi3.0/be/hal_be_tx.h | 186 ++++++------ 8 files changed, 445 insertions(+), 441 deletions(-) diff --git a/hal/wifi3.0/be/hal_be_api.h b/hal/wifi3.0/be/hal_be_api.h index 832134bb42..346b369efa 100644 --- a/hal/wifi3.0/be/hal_be_api.h +++ b/hal/wifi3.0/be/hal_be_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -31,8 +31,8 @@ RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) /** * hal_reo_setup_generic_be - Initialize HW REO block * - * @hal_soc: Opaque HAL SOC handle - * @reo_params: parameters needed by HAL for REO config + * @soc: Opaque HAL SOC handle + * @reoparams: parameters needed by HAL for REO config * @qref_reset: reset qref */ void hal_reo_setup_generic_be(struct hal_soc *soc, @@ -62,21 +62,37 @@ void hal_set_link_desc_addr_be(void *desc, uint32_t cookie, uint8_t bm_id); /** - * hal_hw_txrx_default_ops_attach_be(): Add default ops for BE chips - * @ hal_soc_hdl: hal_soc handle + * hal_hw_txrx_default_ops_attach_be() - Add default ops for BE chips + * @soc: hal_soc handle * * Return: None */ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc); uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc); + +/** + * hal_rx_ret_buf_manager_get_be() - Get return buffer manager from ring desc + * @ring_desc: ring descriptor + * + * Return: rbm + */ uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc); + +/** + * hal_rx_wbm_err_info_get_generic_be() - Retrieves WBM error code and reason and + * save it to hal_wbm_err_desc_info structure passed by caller + * @wbm_desc: wbm ring descriptor + * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. + * + * Return: void + */ void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1); /** - * hal_reo_qdesc_setup - Setup HW REO queue descriptor - * - * @hal_soc: Opaque HAL SOC handle + * hal_reo_qdesc_setup_be() - Setup HW REO queue descriptor + * @hal_soc_hdl: Opaque HAL SOC handle + * @tid: TID * @ba_window_size: BlockAck window size * @start_seq: Starting sequence number * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory @@ -93,7 +109,7 @@ void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, /** * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register * for REO/WBM - * @soc: HAL soc handle + * @hal_soc_hdl: Handle to HAL SoC structure * @cc_cfg: structure pointer for HW cookie conversion configuration * * Return: None @@ -102,13 +118,12 @@ void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl, struct hal_hw_cc_config *cc_cfg); /** - * hal_reo_ix_remap_value_get() - Calculate reo remap register value from - * ring_id_mask which is used for hash based - * reo distribution - * - * @hal_soc: Handle to HAL SoC structure - * @ring_id_mask: mask value indicating the rx rings 0th bit set indicate - * REO2SW1 is included in hash distribution + * hal_reo_ix_remap_value_get_be() - Calculate reo remap register value from + * ring_id_mask which is used for hash based + * reo distribution + * @hal_soc_hdl: Handle to HAL SoC structure + * @rx_ring_mask: mask value indicating the rx rings 0th bit set indicate + * REO2SW1 is included in hash distribution * * Return: REO remap value */ @@ -118,8 +133,7 @@ hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl, /** * hal_reo_ring_remap_value_get_be() - return REO remap value - * - * @ring_id: REO2SW ring id + * @rx_ring_id: REO2SW ring mask * * Return: REO remap value */ diff --git a/hal/wifi3.0/be/hal_be_api_mon.h b/hal/wifi3.0/be/hal_be_api_mon.h index 6f4c17041c..305002f383 100644 --- a/hal/wifi3.0/be/hal_be_api_mon.h +++ b/hal/wifi3.0/be/hal_be_api_mon.h @@ -622,12 +622,12 @@ struct hal_rx_status_buffer_done { }; /** - * hal_mon_status_end_reason : ppdu status buffer end reason + * enum hal_mon_status_end_reason - ppdu status buffer end reason * * @HAL_MON_STATUS_BUFFER_FULL: status buffer full * @HAL_MON_FLUSH_DETECTED: flush detected * @HAL_MON_END_OF_PPDU: end of ppdu detected - * HAL_MON_PPDU_truncated: truncated ppdu status + * @HAL_MON_PPDU_TRUNCATED: truncated ppdu status */ enum hal_mon_status_end_reason { HAL_MON_STATUS_BUFFER_FULL, @@ -637,7 +637,7 @@ enum hal_mon_status_end_reason { }; /** - * struct hal_mon_desc () - HAL Monitor descriptor + * struct hal_mon_desc - HAL Monitor descriptor * * @buf_addr: virtual buffer address * @ppdu_id: ppdu id @@ -645,7 +645,9 @@ enum hal_mon_status_end_reason { * - RxMON fills phy_ppdu_id * @end_offset: offset (units in 4 bytes) where status buffer ended * i.e offset of TLV + last TLV size - * @end_reason: 0 - status buffer is full + * @reserved_3a: reserved bits + * @end_reason: ppdu end reason + * 0 - status buffer is full * 1 - flush detected * 2 - TX_FES_STATUS_END or RX_PPDU_END * 3 - PPDU truncated due to system error @@ -658,7 +660,6 @@ enum hal_mon_status_end_reason { * @looping_count: count to indicate number of times producer * of entries has looped around the ring * @flush_detected: if flush detected - * @end_reason: ppdu end reason * @end_of_ppdu_dropped: if end_of_ppdu is dropped * @ppdu_drop_count: PPDU drop count * @mpdu_drop_count: MPDU drop count @@ -684,14 +685,16 @@ struct hal_mon_desc { typedef struct hal_mon_desc *hal_mon_desc_t; /** - * struct hal_mon_buf_addr_status () - HAL buffer address tlv get status + * struct hal_mon_buf_addr_status - HAL buffer address tlv get status * - * @buf_addr_31_0: Lower 32 bits of virtual address of status buffer - * @buf_addr_63_32: Upper 32 bits of virtual address of status buffer + * @buffer_virt_addr_31_0: Lower 32 bits of virtual address of status buffer + * @buffer_virt_addr_63_32: Upper 32 bits of virtual address of status buffer * @dma_length: DMA length + * @reserved_2a: reserved bits * @msdu_continuation: is msdu size more than fragment size * @truncated: is msdu got truncated - * @tlv_padding: tlv paddding + * @reserved_2b: reserved bits + * @tlv64_padding: tlv paddding */ struct hal_mon_buf_addr_status { uint32_t buffer_virt_addr_31_0; @@ -706,9 +709,10 @@ struct hal_mon_buf_addr_status { #ifdef QCA_MONITOR_2_0_SUPPORT /** - * hal_be_get_mon_dest_status() - Get monitor descriptor - * @hal_soc_hdl: HAL Soc handle - * @desc: HAL monitor descriptor + * hal_be_get_mon_dest_status() - Get monitor descriptor status + * @hal_soc: HAL Soc handle + * @hw_desc: HAL monitor descriptor + * @status: pointer to write descriptor status * * Return: none */ @@ -950,7 +954,8 @@ hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, * hal_mon_buff_addr_info_set() - set desc address in cookie * @hal_soc_hdl: HAL Soc handle * @mon_entry: monitor srng - * @desc: HAL monitor descriptor + * @mon_desc_addr: HAL monitor descriptor virtual address + * @phy_addr: HAL monitor descriptor physical address * * Return: none */ @@ -1087,6 +1092,11 @@ enum txmon_generated_response { * @transmission_type: su or mu transmission type * @medium_prot_type: medium protection type * @generated_response: Generated frame in response window + * @band_center_freq1: + * @band_center_freq2: + * @freq: + * @phy_mode: + * @schedule_id: * @no_bitmap_avail: Bitmap available flag * @explicit_ack: Explicit Acknowledge flag * @explicit_ack_type: Explicit Acknowledge type @@ -1094,8 +1104,13 @@ enum txmon_generated_response { * @response_type: Response type in response window * @ndp_frame: NDP frame * @num_users: number of users + * @reserved: reserved bits + * @mba_count: MBA count + * @mba_fake_bitmap_count: MBA fake bitmap count * @sw_frame_group_id: software frame group ID * @r2r_to_follow: Response to Response follow flag + * @phy_abort_reason: Reason for PHY abort + * @phy_abort_user_number: User number for PHY abort * @buffer: Packet buffer pointer address * @offset: Packet buffer offset * @length: Packet buffer length @@ -1194,7 +1209,7 @@ hal_tx_status_get_next_tlv(uint8_t *tx_tlv) { /** * hal_txmon_status_parse_tlv() - process transmit info TLV - * @hal_soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @data_ppdu_info: pointer to hal data ppdu info * @prot_ppdu_info: pointer to hal prot ppdu info * @data_status_info: pointer to data status info @@ -1226,7 +1241,7 @@ hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, /** * hal_txmon_status_get_num_users() - api to get num users from start of fes * window - * @hal_soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @tx_tlv_hdr: pointer to TLV header * @num_users: reference to number of user * @@ -1261,7 +1276,7 @@ hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) /** * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv - * @hal_soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @tx_tlv_hdr: pointer to TLV header * * Return: bool @@ -1279,7 +1294,7 @@ hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) /** * hal_txmon_populate_packet_info() - api to populate packet info - * @hal_soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @tx_tlv_hdr: pointer to TLV header * @packet_info: pointer to placeholder for packet info * @@ -2210,9 +2225,11 @@ hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ /** - * hal_rx_status_get_tlv_info() - process receive info TLV + * hal_rx_status_get_tlv_info_generic_be() - process receive info TLV * @rx_tlv_hdr: pointer to TLV header - * @ppdu_info: pointer to ppdu_info + * @ppduinfo: pointer to ppdu_info + * @hal_soc_hdl: HAL version of the SOC pointer + * @nbuf: Network buffer * * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv */ diff --git a/hal/wifi3.0/be/hal_be_generic_api.c b/hal/wifi3.0/be/hal_be_generic_api.c index 4c59223609..8a5930462c 100644 --- a/hal/wifi3.0/be/hal_be_generic_api.c +++ b/hal/wifi3.0/be/hal_be_generic_api.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -75,7 +75,7 @@ void hal_setup_reo_swap(struct hal_soc *soc) /** * hal_tx_init_data_ring_be() - Initialize all the TCL Descriptors in SRNG * @hal_soc_hdl: Handle to HAL SoC structure - * @hal_srng: Handle to HAL SRNG structure + * @hal_ring_hdl: Handle to HAL SRNG structure * * Return: none */ @@ -326,12 +326,6 @@ static uint32_t hal_rx_wbm_err_src_get_be(hal_ring_desc_t ring_desc) HAL_BE_WBM_RELEASE_DIR_RX); } -/** - * hal_rx_ret_buf_manager_get_be() - Get return buffer manager from ring desc - * @ring_desc: ring descriptor - * - * Return: rbm - */ uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc) { /* @@ -364,13 +358,6 @@ uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc) WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK) >> \ WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB) -/** - * hal_rx_wbm_err_info_get_generic_be(): Retrieves WBM error code and reason and - * save it to hal_wbm_err_desc_info structure passed by caller - * @wbm_desc: wbm ring descriptor - * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. - * Return: void - */ void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1) { struct hal_wbm_err_desc_info *wbm_er_info = @@ -441,13 +428,11 @@ static void hal_rx_msdu_link_desc_set_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_rx_reo_ent_buf_paddr_get_be: Gets the physical address and - * cookie from the REO entrance ring element + * hal_rx_buf_cookie_rbm_get_be() - Get the cookie and return buffer + * manager from the REO entrance ring desc + * @buf_addr_info_hdl: Buffer address info element from ring desc + * @buf_info_hdl: structure to return the buffer information * - * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to - * the current descriptor - * @ buf_info: structure to return the buffer information - * @ msdu_cnt: pointer to msdu count in MPDU * Return: void */ static @@ -468,7 +453,7 @@ void hal_rx_buf_cookie_rbm_get_be(uint32_t *buf_addr_info_hdl, (hal_ring_desc_t)buf_addr_info); } -/* +/** * hal_rxdma_buff_addr_info_set_be() - set the buffer_addr_info of the * rxdma ring entry. * @rxdma_entry: descriptor entry @@ -507,6 +492,7 @@ static uint32_t hal_rx_get_reo_error_code_be(hal_ring_desc_t rx_desc) /** * hal_gen_reo_remap_val_generic_be() - Generate the reo map value + * @remap_reg: remap register * @ix0_map: mapping values for reo * * Return: IX0 reo remap register value to be written @@ -681,9 +667,9 @@ hal_mpdu_desc_info_set_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_rx_msdu_reo_dst_ind_get: Gets the REO - * destination ring ID from the msdu desc info - * + * hal_rx_msdu_reo_dst_ind_get_be() - Gets the REO destination ring ID + * from the msdu desc info + * @hal_soc_hdl: hal_soc handle * @msdu_link_desc : Opaque cookie pointer used by HAL to get to * the current descriptor * @@ -809,7 +795,7 @@ hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc, #ifdef DP_UMAC_HW_RESET_SUPPORT /** * hal_unregister_reo_send_cmd_be() - Unregister Reo send command callback. - * @hal_soc_hdl: HAL soc handle + * @hal_soc: HAL soc handle * * Return: None */ @@ -821,7 +807,7 @@ void hal_unregister_reo_send_cmd_be(struct hal_soc *hal_soc) /** * hal_register_reo_send_cmd_be() - Register Reo send command callback. - * @hal_soc_hdl: HAL soc handle + * @hal_soc: HAL soc handle * * Return: None */ @@ -833,9 +819,9 @@ void hal_register_reo_send_cmd_be(struct hal_soc *hal_soc) /** * hal_reset_rx_reo_tid_q_be() - reset the reo tid queue. - * @hal_soc_hdl: HAL soc handle - * @hw_qdesc_vaddr:start address of the tid queue - * @size:size of address pointed by hw_qdesc_vaddr + * @hal_soc: HAL soc handle + * @hw_qdesc_vaddr: start address of the tid queue + * @size: size of address pointed by hw_qdesc_vaddr * * Return: None */ @@ -928,13 +914,6 @@ hal_reset_rx_reo_tid_q_be(struct hal_soc *hal_soc, void *hw_qdesc_vaddr, } #endif -/** - * hal_hw_txrx_default_ops_attach_be() - Attach the default hal ops for - * beryllium chipsets. - * @hal_soc_hdl: HAL soc handle - * - * Return: None - */ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc) { hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_be; diff --git a/hal/wifi3.0/be/hal_be_generic_api.h b/hal/wifi3.0/be/hal_be_generic_api.h index 7a086e9fd6..f7f826075f 100644 --- a/hal/wifi3.0/be/hal_be_generic_api.h +++ b/hal/wifi3.0/be/hal_be_generic_api.h @@ -27,7 +27,7 @@ #include #include "txmon_tlvs.h" -/** +/* * Debug macro to print the TLV header tag */ #define SHOW_DEFINED(x) do {} while (0) @@ -49,8 +49,10 @@ hal_tx_comp_get_buffer_timestamp_be(void *desc, #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */ /** - * hal_tx_comp_get_status() - TQM Release reason - * @hal_desc: completion ring Tx status + * hal_tx_comp_get_status_generic_be() - TQM Release reason + * @desc: WBM descriptor + * @ts1: completion ring Tx status + * @hal: hal_soc * * This function will parse the WBM completion descriptor and populate in * HAL structure @@ -187,7 +189,7 @@ hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, /** * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority * @soc: HAL SoC context - * @val: priority value + * @value: priority value * * Return: void */ @@ -220,9 +222,9 @@ static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, /** * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST - * @fst: Pointer to the Rx Flow Search Table + * @rx_fst: Pointer to the Rx Flow Search Table * @hal_hash: HAL 5 tuple hash - * @tuple_info: 5-tuple info of the flow returned to the caller + * @flow_tuple_info: 5-tuple info of the flow returned to the caller * * Return: Success/Failure */ @@ -291,7 +293,7 @@ hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash, /** * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST - * @fst: Pointer to the Rx Flow Search Table + * @rx_fst: Pointer to the Rx Flow Search Table * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST * * Return: Success/Failure @@ -327,7 +329,7 @@ hal_rx_fst_get_fse_size_be(void) #ifdef QCA_MONITOR_2_0_SUPPORT /** * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv - * @tx_tlv: pointer to TLV header + * @tx_tlv_hdr: pointer to TLV header * * Return: bool based on tlv tag matches monitor buffer address tlv */ @@ -385,7 +387,7 @@ hal_txmon_get_num_users(void *tx_tlv) * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv * * @tx_tlv: pointer to tx_fes_setup tlv header - * @ppdu_info: pointer to hal_tx_ppdu_info + * @tx_ppdu_info: pointer to hal_tx_ppdu_info * * Return: void */ @@ -487,7 +489,7 @@ hal_txmon_get_num_users(void *tx_tlv) * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv * * @tx_tlv: pointer to tx_fes_setup tlv header - * @ppdu_info: pointer to hal_tx_ppdu_info + * @tx_ppdu_info: pointer to hal_tx_ppdu_info * * Return: void */ @@ -685,7 +687,7 @@ uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx) * * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header * @type: place where this tlv is generated - * @tx_status_info: pointer to hal_tx_status_info + * @status_info: pointer to hal_tx_status_info * * Return: void */ @@ -782,9 +784,8 @@ hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users) /** * hal_tx_get_ppdu_info() - api to get tx ppdu info - * @pdev_handle: DP_PDEV handle - * @prot_ppdu_info: populate dp_ppdu_info protection - * @tx_data_ppdu_info: populate dp_ppdu_info data + * @data_info: populate dp_ppdu_info data + * @prot_info: populate dp_ppdu_info protection * @tlv_tag: Tag * * Return: dp_tx_ppdu_info pointer @@ -2966,11 +2967,12 @@ static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue + * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue * reference table shared between SW and HW and initialize in Qdesc Base0 * base1 registers provided by HW. * - * @hal_soc: HAL Soc handle + * @hal_soc_hdl: HAL Soc handle + * @reo_qref: REO queue reference table * * Return: QDF_STATUS_SUCCESS on success else a QDF error. */ @@ -3019,10 +3021,10 @@ hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and + * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and * write start addr of MLO and Non MLO table in HW * - * @hal_soc: HAL Soc handle + * @hal_soc_hdl: HAL Soc handle * @qref_reset: reset qref LUT * * Return: None @@ -3059,10 +3061,10 @@ static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue + * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue * reference table shared between SW and HW * - * @hal_soc: HAL Soc handle + * @hal_soc_hdl: HAL Soc handle * * Return: None */ @@ -3080,8 +3082,8 @@ static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) #endif /** - * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing - * @hal_soc: HAL SoC context + * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing + * @hal_soc_hdl: HAL SoC context * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW * @@ -3120,8 +3122,8 @@ hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, #endif /** - * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing - * @hal_soc: HAL SoC context + * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing + * @hal_soc_hdl: HAL SoC context * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM * @@ -3159,9 +3161,9 @@ hal_tx_mcast_mlo_reinject_routing_set_generic_be( #endif /** - * hal_get_ba_aging_timeout_be - Get BA Aging timeout + * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout * - * @hal_soc: Opaque HAL SOC handle + * @hal_soc_hdl: Opaque HAL SOC handle * @ac: Access category * @value: window size to get */ @@ -3203,7 +3205,7 @@ void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the * buffer list provided * - * @hal_soc: Opaque HAL SOC handle + * @soc: Opaque HAL SOC handle * @scatter_bufs_base_paddr: Array of physical base addresses * @scatter_bufs_base_vaddr: Array of virtual base addresses * @num_scatter_bufs: Number of scatter buffers in the above lists @@ -3355,7 +3357,7 @@ hal_setup_link_idle_list_generic_be(struct hal_soc *soc, /** * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register * for REO/WBM - * @soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @cc_cfg: structure pointer for HW cookie conversion configuration * * Return: None @@ -3486,9 +3488,8 @@ void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, } /** - * hal_set_ba_aging_timeout_be - Set BA Aging timeout - * - * @hal_soc: Opaque HAL SOC handle + * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout + * @hal_soc_hdl: Opaque HAL SOC handle * @ac: Access category * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice * @value: Input value to set @@ -3531,9 +3532,9 @@ void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, } /** - * hal_tx_populate_bank_register() - populate the bank register with + * hal_tx_populate_bank_register_be() - populate the bank register with * the software configs. - * @soc: HAL soc handle + * @hal_soc_hdl: HAL soc handle * @config: bank config * @bank_id: bank id to be configured * @@ -3626,8 +3627,9 @@ hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 /** - * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value - * @hal_soc: HAL SoC context + * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value + * @hal_soc_hdl: HAL SoC context + * @vdev_id: vdev identifier * @mcast_ctrl_val: mcast ctrl value for this VAP * * Return: void diff --git a/hal/wifi3.0/be/hal_be_reo.c b/hal/wifi3.0/be/hal_be_reo.c index 9bcfc7076f..703d4ac9c1 100644 --- a/hal/wifi3.0/be/hal_be_reo.c +++ b/hal/wifi3.0/be/hal_be_reo.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -29,17 +29,6 @@ uint32_t hal_get_reo_reg_base_offset_be(void) return REO_REG_REG_BASE; } -/** - * hal_reo_qdesc_setup - Setup HW REO queue descriptor - * - * @hal_soc: Opaque HAL SOC handle - * @ba_window_size: BlockAck window size - * @start_seq: Starting sequence number - * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory - * @hw_qdesc_paddr: Physical address of REO queue descriptor memory - * @tid: TID - * - */ void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, int tid, uint32_t ba_window_size, uint32_t start_seq, void *hw_qdesc_vaddr, diff --git a/hal/wifi3.0/be/hal_be_reo.h b/hal/wifi3.0/be/hal_be_reo.h index 93cbca56d0..6a1ff9d73d 100644 --- a/hal/wifi3.0/be/hal_be_reo.h +++ b/hal/wifi3.0/be/hal_be_reo.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -82,8 +82,8 @@ hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc, /** * hal_reo_init_cmd_ring_be() - Initialize descriptors of REO command SRNG * with command number - * @hal_soc: Handle to HAL SoC structure - * @hal_ring: Handle to HAL SRNG structure + * @hal_soc_hdl: Handle to HAL SoC structure + * @hal_ring_hdl: Handle to HAL SRNG structure * * Return: none */ diff --git a/hal/wifi3.0/be/hal_be_rx_tlv.h b/hal/wifi3.0/be/hal_be_rx_tlv.h index 58b28eeabc..3f31bd85ea 100644 --- a/hal/wifi3.0/be/hal_be_rx_tlv.h +++ b/hal/wifi3.0/be/hal_be_rx_tlv.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -601,9 +601,9 @@ struct rx_mon_pkt_tlvs { HAL_RX_MSDU_END(_rx_pkt_tlv).mcast_bcast #ifdef RECEIVE_OFFLOAD -/** -* LRO information needed from the TLVs -*/ +/* + * LRO information needed from the TLVs + */ #define HAL_RX_TLV_GET_LRO_ELIGIBLE(_rx_pkt_tlv) \ HAL_RX_MSDU_END(_rx_pkt_tlv).lro_eligible @@ -811,11 +811,11 @@ static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf) return HAL_RX_TLV_MSDU_DONE_GET(buf); } -/* - * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention +/** + * hal_rx_tlv_first_mpdu_get_be() - get first_mpdu bit from rx attention * @buf: pointer to rx_pkt_tlvs * - * return: uint32_t(first_msdu) + * Return: uint32_t(first_msdu) */ static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf) { @@ -824,10 +824,10 @@ static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf) return HAL_RX_TLV_FIRST_MPDU_GET(rx_pkt_tlvs); } -/* - * hal_rx_msdu_cce_match_get(): get CCE match bit - * from rx attention +/** + * hal_rx_msdu_cce_match_get_be() - get CCE match bit from rx attention * @buf: pointer to rx_pkt_tlvs + * * Return: CCE match value */ static inline bool hal_rx_msdu_cce_match_get_be(uint8_t *buf) @@ -850,11 +850,11 @@ static inline uint32_t hal_rx_msdu_peer_meta_data_get_be(uint8_t *buf) } #endif -/* - * hal_rx_mpdu_get_addr1_be(): API to check get address1 of the mpdu - * +/** + * hal_rx_mpdu_get_addr1_be() - API to check get address1 of the mpdu * @buf: pointer to the start of RX PKT TLV headera * @mac_addr: pointer to mac address + * * Return: success/failure */ static inline QDF_STATUS hal_rx_mpdu_get_addr1_be(uint8_t *buf, @@ -882,7 +882,7 @@ static inline QDF_STATUS hal_rx_mpdu_get_addr1_be(uint8_t *buf, #ifndef CONFIG_WORD_BASED_TLV /** - * hal_rx_mpdu_info_ampdu_flag_get_be(): get ampdu flag bit + * hal_rx_mpdu_info_ampdu_flag_get_be() - get ampdu flag bit * from rx mpdu info * @buf: pointer to rx_pkt_tlvs * @@ -896,7 +896,7 @@ static inline bool hal_rx_mpdu_info_ampdu_flag_get_be(uint8_t *buf) } /** - * hal_rx_get_qdesc_addr_be(): API to get qdesc address of reo + * hal_rx_get_qdesc_addr_be() - API to get qdesc address of reo * entrance ring desc * * @dst_ring_desc: reo dest ring descriptor (used for Lithium DP) @@ -911,11 +911,11 @@ static inline uint64_t hal_rx_get_qdesc_addr_be(uint8_t *dst_ring_desc, return (uint64_t)HAL_RX_REO_QUEUE_DESC_ADDR_31_0_GET(rx_pkt_tlvs); } -/* - * @ hal_rx_print_pn_be: Prints the PN of rx packet. +/** + * hal_rx_print_pn_be() - Prints the PN of rx packet. + * @buf: rx_tlv_hdr of the received packet * - * @ buf: rx_tlv_hdr of the received packet - * @ Return: void + * Return: void */ static inline void hal_rx_print_pn_be(uint8_t *buf) { @@ -941,12 +941,12 @@ static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) pn_num[1] |= ((uint64_t)HAL_RX_TLV_MPDU_PN_127_96_GET(pkt_tlvs) << 32); } -/* - * hal_rx_mpdu_get_addr4_be(): API to get address4 of the mpdu +/** + * hal_rx_mpdu_get_addr4_be() - API to get address4 of the mpdu * in the packet - * * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address + * * Return: success/failure */ static inline QDF_STATUS hal_rx_mpdu_get_addr4_be(uint8_t *buf, @@ -972,7 +972,7 @@ static inline QDF_STATUS hal_rx_mpdu_get_addr4_be(uint8_t *buf, } /** - * hal_rx_priv_info_set_in_tlv_be(): Save the private info to + * hal_rx_priv_info_set_in_tlv_be() - Save the private info to * the reserved bytes of rx_tlv_hdr * @buf: start of rx_tlv_hdr * @priv_data: hal_wbm_err_desc_info structure @@ -991,7 +991,7 @@ static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, } /** - * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from + * hal_rx_priv_info_get_from_tlv_be() - retrieve the private data from * the reserved bytes of rx_tlv_hdr. * @buf: start of rx_tlv_hdr * @priv_data: Handle to get the private data, output parameter. @@ -1010,10 +1010,10 @@ static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, } /** - * hal_rx_tlv_l3_type_get_be(): API to get the l3 type - * from rx_msdu_start TLV - * + * hal_rx_tlv_l3_type_get_be() - API to get the l3 type from + * rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers + * * Return: uint32_t(l3 type) */ static inline uint32_t hal_rx_tlv_l3_type_get_be(uint8_t *buf) @@ -1024,7 +1024,7 @@ static inline uint32_t hal_rx_tlv_l3_type_get_be(uint8_t *buf) } /** - * hal_rx_hw_desc_get_ppduid_get_be(): retrieve ppdu id + * hal_rx_hw_desc_get_ppduid_get_be() - retrieve ppdu id * @rx_tlv_hdr: start address of rx_pkt_tlvs * @rxdma_dst_ring_desc: Rx HW descriptor * @@ -1039,8 +1039,8 @@ hal_rx_hw_desc_get_ppduid_get_be(void *rx_tlv_hdr, void *rxdma_dst_ring_desc) return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); } -/* - * hal_rx_tlv_phy_ppdu_id_get(): get phy_ppdu_id value +/** + * hal_rx_tlv_phy_ppdu_id_get_be() - get phy_ppdu_id value * from rx attention * @buf: pointer to rx_pkt_tlvs * @@ -1053,8 +1053,8 @@ static inline uint16_t hal_rx_tlv_phy_ppdu_id_get_be(uint8_t *buf) return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); } -/* - * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value +/** + * hal_rx_attn_phy_ppdu_id_get_be() - get phy_ppdu_id value * from rx attention * @buf: pointer to rx_pkt_tlvs * @@ -1078,11 +1078,11 @@ hal_rx_get_ppdu_id_be(uint8_t *buf) return HAL_RX_GET_PPDU_ID(rx_pkt_tlvs); } -/* - * hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv - * +/** + * hal_rx_mpdu_peer_meta_data_set_be() - set peer meta data in RX mpdu start tlv * @buf: rx_tlv_hdr of the received packet * @peer_mdata: peer meta data to be set. + * * Return: void */ static inline void @@ -1112,9 +1112,9 @@ static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf) } /** - * hal_rx_is_unicast_be: check packet is unicast frame or not. + * hal_rx_is_unicast_be() - check packet is unicast frame or not. + * @buf: pointer to rx pkt TLV. * - * @ buf: pointer to rx pkt TLV. * Return: true on unicast. */ static inline bool hal_rx_is_unicast_be(uint8_t *buf) @@ -1129,12 +1129,6 @@ static inline bool hal_rx_is_unicast_be(uint8_t *buf) #else #define IS_ADDR_MULTICAST(_a) (*(_a) & 0x01) -/** - * hal_rx_is_unicast_be: check packet is unicast frame or not. - * - * @ buf: pointer to rx pkt TLV. - * Return: true on unicast. - */ static inline bool hal_rx_is_unicast_be(uint8_t *buf) { uint8_t mac[QDF_MAC_ADDR_SIZE] = {0}; @@ -1145,11 +1139,12 @@ static inline bool hal_rx_is_unicast_be(uint8_t *buf) } /** - * hal_rx_priv_info_set_in_tlv_be(): Save the private info to + * hal_rx_priv_info_set_in_tlv_be() - Save the private info to * the reserved bytes of rx_tlv_hdr * @buf: start of rx_tlv_hdr * @priv_data: hal_wbm_err_desc_info structure * @len: length of the private data + * * Return: void */ static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, @@ -1165,11 +1160,12 @@ static inline void hal_rx_priv_info_set_in_tlv_be(uint8_t *buf, } /** - * hal_rx_priv_info_get_from_tlv_be(): retrieve the private data from + * hal_rx_priv_info_get_from_tlv_be() - retrieve the private data from * the reserved bytes of rx_tlv_hdr. * @buf: start of rx_tlv_hdr * @priv_data: Handle to get the private data, output parameter. * @len: length of the private data + * * Return: void */ static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, @@ -1185,11 +1181,11 @@ static inline void hal_rx_priv_info_get_from_tlv_be(uint8_t *buf, copy_len); } -/* - * @ hal_rx_print_pn_be: Prints the PN of rx packet. +/** + * hal_rx_print_pn_be() - Prints the PN of rx packet. + * @buf: rx_tlv_hdr of the received packet * - * @ buf: rx_tlv_hdr of the received packet - * @ Return: void + * Return: void */ static inline void hal_rx_print_pn_be(uint8_t *buf) { @@ -1215,10 +1211,10 @@ static inline void hal_rx_tlv_get_pn_num_be(uint8_t *buf, uint64_t *pn_num) #endif /** - * hal_rx_tlv_msdu_len_get(): API to get the MSDU length - * from rx_msdu_start TLV + * hal_rx_tlv_msdu_len_get_be() - API to get the MSDU length from + * rx_msdu_start TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: msdu length */ static inline uint32_t hal_rx_tlv_msdu_len_get_be(uint8_t *buf) @@ -1228,10 +1224,9 @@ static inline uint32_t hal_rx_tlv_msdu_len_get_be(uint8_t *buf) return HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); } - /** - * hal_rx_tlv_msdu_len_set(): API to set the MSDU length - * from rx_msdu_start TLV - * +/** + * hal_rx_tlv_msdu_len_set_be() - API to set the MSDU length from + * rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers * @len: msdu length * @@ -1244,11 +1239,11 @@ static inline void hal_rx_tlv_msdu_len_set_be(uint8_t *buf, uint32_t len) HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs) = len; } -/* - * hal_rx_tlv_bw_get(): API to get the Bandwidth - * Interval from rx_msdu_start - * +/** + * hal_rx_tlv_bw_get_be() - API to get the Bandwidth Interval from + * rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(bw) */ static inline uint32_t hal_rx_tlv_bw_get_be(uint8_t *buf) @@ -1258,11 +1253,11 @@ static inline uint32_t hal_rx_tlv_bw_get_be(uint8_t *buf) return HAL_RX_TLV_BW_GET(rx_pkt_tlvs); } - /** - * hal_rx_tlv_toeplitz_get: API to get the toeplitz hash - * from rx_msdu_start TLV +/** + * hal_rx_tlv_toeplitz_get_be() - API to get the toeplitz hash from + * rx_msdu_start TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: toeplitz hash */ static inline uint32_t hal_rx_tlv_toeplitz_get_be(uint8_t *buf) @@ -1273,10 +1268,10 @@ static inline uint32_t hal_rx_tlv_toeplitz_get_be(uint8_t *buf) } /** - * hal_rx_tlv_msdu_sgi_get(): API to get the Short Guard - * Interval from rx_msdu_start TLV - * + * hal_rx_tlv_sgi_get_be() - API to get the Short Guard Interval from + * rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers + * * Return: uint32_t(sgi) */ static inline uint32_t hal_rx_tlv_sgi_get_be(uint8_t *buf) @@ -1287,10 +1282,10 @@ static inline uint32_t hal_rx_tlv_sgi_get_be(uint8_t *buf) } /** - * hal_rx_tlv_msdu_rate_mcs_get(): API to get the MCS rate - * from rx_msdu_start TLV - * + * hal_rx_tlv_rate_mcs_get_be() - API to get the MCS rate from + * rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers + * * Return: uint32_t(rate_mcs) */ static inline uint32_t hal_rx_tlv_rate_mcs_get_be(uint8_t *buf) @@ -1303,14 +1298,11 @@ static inline uint32_t hal_rx_tlv_rate_mcs_get_be(uint8_t *buf) return rate_mcs; } -/* - * Get key index from RX_MSDU_END - */ -/* - * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet - * from rx_msdu_end - * +/** + * hal_rx_msdu_get_keyid_be() - API to get the key id of the decrypted packet + * from rx_msdu_end * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(key id) */ @@ -1324,11 +1316,11 @@ static inline uint8_t hal_rx_msdu_get_keyid_be(uint8_t *buf) return keyid_octet & 0x3; } -/* - * hal_rx_tlv_get_rssi(): API to get the rssi of received pkt - * from rx_msdu_start - * +/** + * hal_rx_tlv_get_rssi_be() - API to get the rssi of received pkt from + * rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(rssi) */ @@ -1342,11 +1334,11 @@ static inline uint32_t hal_rx_tlv_get_rssi_be(uint8_t *buf) return rssi; } -/* - * hal_rx_tlv_get_freq(): API to get the frequency of operating channel - * from rx_msdu_start - * +/** + * hal_rx_tlv_get_freq_be() - API to get the frequency of operating + * channel from rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(frequency) */ @@ -1361,11 +1353,11 @@ static inline uint32_t hal_rx_tlv_get_freq_be(uint8_t *buf) } -/* - * hal_rx_tlv_get_pkt_type(): API to get the pkt type - * from rx_msdu_start - * +/** + * hal_rx_tlv_get_pkt_type_be() - API to get the pkt type from + * rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(pkt type) */ @@ -1384,10 +1376,10 @@ static inline uint32_t hal_rx_tlv_get_pkt_type_be(uint8_t *buf) ******************************************************************************/ /** - * hal_rx_tlv_decrypt_err_get(): API to get the Decrypt ERR - * from rx_mpdu_end TLV - * + * hal_rx_tlv_decrypt_err_get_be() - API to get the Decrypt ERR from + * rx_mpdu_end TLV * @buf: pointer to the start of RX PKT TLV headers + * * Return: uint32_t(decrypt_err) */ static inline uint32_t hal_rx_tlv_decrypt_err_get_be(uint8_t *buf) @@ -1401,10 +1393,9 @@ static inline uint32_t hal_rx_tlv_decrypt_err_get_be(uint8_t *buf) } /** - * hal_rx_tlv_mic_err_get(): API to get the MIC ERR - * from rx_tlv TLV - * + * hal_rx_tlv_mic_err_get_be() - API to get the MIC ERR from rx_tlv TLV * @buf: pointer to the start of RX PKT TLV headers + * * Return: uint32_t(mic_err) */ static inline uint32_t hal_rx_tlv_mic_err_get_be(uint8_t *buf) @@ -1418,10 +1409,10 @@ static inline uint32_t hal_rx_tlv_mic_err_get_be(uint8_t *buf) } /** - * hal_get_reo_ent_desc_qdesc_addr_be(): API to get qdesc address of reo - * entrance ring desc - * + * hal_get_reo_ent_desc_qdesc_addr_be() - API to get qdesc address of + * reo entrance ring desc * @desc: reo entrance ring descriptor + * * Return: qdesc address */ static inline uint8_t *hal_get_reo_ent_desc_qdesc_addr_be(uint8_t *desc) @@ -1430,11 +1421,11 @@ static inline uint8_t *hal_get_reo_ent_desc_qdesc_addr_be(uint8_t *desc) } /** - * hal_set_reo_ent_desc_reo_dest_ind_be(): API to set reo destination - * indication of reo entrance ring desc - * + * hal_set_reo_ent_desc_reo_dest_ind_be() - API to set reo destination + * indication of reo entrance ring desc * @desc: reo ent ring descriptor * @dst_ind: reo destination indication value + * * Return: None */ static inline void @@ -1445,7 +1436,7 @@ hal_set_reo_ent_desc_reo_dest_ind_be(uint8_t *desc, uint32_t dst_ind) } /** - * hal_rx_mpdu_sequence_number_get() - Get mpdu sequence number + * hal_rx_mpdu_sequence_number_get_be() - Get mpdu sequence number * @buf: pointer to packet buffer * * Return: mpdu sequence @@ -1458,11 +1449,11 @@ static inline int hal_rx_mpdu_sequence_number_get_be(uint8_t *buf) } /** - * hal_rx_msdu_packet_metadata_get(): API to get the - * msdu information from rx_msdu_end TLV - * - * @ buf: pointer to the start of RX PKT TLV headers - * @ hal_rx_msdu_metadata: pointer to the msdu info structure + * hal_rx_msdu_packet_metadata_get_generic_be() - API to get the msdu + * information from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * @pkt_msdu_metadata: pointer to the msdu info structure */ static inline void hal_rx_msdu_packet_metadata_get_generic_be(uint8_t *buf, @@ -1480,11 +1471,11 @@ hal_rx_msdu_packet_metadata_get_generic_be(uint8_t *buf, HAL_RX_TLV_SA_SW_PEER_ID_GET(rx_pkt_tlvs); } -/* - * hal_rx_msdu_start_nss_get_kiwi(): API to get the NSS - * Interval from rx_msdu_start - * +/** + * hal_rx_tlv_nss_get_be() - API to get the NSS Interval from + * rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(nss) */ static inline uint32_t hal_rx_tlv_nss_get_be(uint8_t *buf) @@ -1521,10 +1512,9 @@ static inline uint32_t hal_rx_tlv_nss_get_be(uint8_t *buf) #endif /** - * hal_rx_mon_hw_desc_get_mpdu_status_be(): Retrieve MPDU status - * - * @ hw_desc_addr: Start address of Rx HW TLVs - * @ rs: Status for monitor mode + * hal_rx_mon_hw_desc_get_mpdu_status_be() - Retrieve MPDU status + * @hw_desc_addr: Start address of Rx HW TLVs + * @rs: Status for monitor mode * * Return: void */ @@ -1565,11 +1555,11 @@ static inline uint32_t hal_rx_tlv_tid_get_be(uint8_t *buf) return tid; } -/* - * hal_rx_tlv_reception_type_get(): API to get the reception type - * Interval from rx_msdu_start - * +/** + * hal_rx_tlv_reception_type_get_be() - API to get the reception type + * Interval from rx_msdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(reception_type) */ static inline @@ -1584,10 +1574,10 @@ uint32_t hal_rx_tlv_reception_type_get_be(uint8_t *buf) } /** - * hal_rx_msdu_end_da_idx_get_be: API to get da_idx - * from rx_msdu_end TLV + * hal_rx_msdu_end_da_idx_get_be() - API to get da_idx from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: da index */ static inline uint16_t hal_rx_msdu_end_da_idx_get_be(uint8_t *buf) @@ -1601,10 +1591,10 @@ static inline uint16_t hal_rx_msdu_end_da_idx_get_be(uint8_t *buf) } /** - * hal_rx_get_rx_fragment_number_be(): Function to retrieve rx fragment number + * hal_rx_get_rx_fragment_number_be() - Function to retrieve rx fragment number + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: rx fragment number + * Return: rx fragment number */ static inline uint8_t hal_rx_get_rx_fragment_number_be(uint8_t *buf) @@ -1617,10 +1607,10 @@ uint8_t hal_rx_get_rx_fragment_number_be(uint8_t *buf) } /** - * hal_rx_msdu_end_da_is_mcbc_get_be(): API to check if pkt is MCBC - * from rx_msdu_end TLV + * hal_rx_tlv_da_is_mcbc_get_be() - API to check if pkt is MCBC from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: da_is_mcbc */ static inline uint8_t @@ -1632,10 +1622,10 @@ hal_rx_tlv_da_is_mcbc_get_be(uint8_t *buf) } /** - * hal_rx_tlv_is_tkip_mic_err_get_be(): API to get tkip Mic error - * from rx_msdu_end TLV + * hal_rx_tlv_is_tkip_mic_err_get_be() - API to get tkip Mic error + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: tkip_mic_err */ static inline uint8_t @@ -1647,10 +1637,10 @@ hal_rx_tlv_is_tkip_mic_err_get_be(uint8_t *buf) } /** - * hal_rx_tlvd_sa_is_valid_get_be(): API to get the sa_is_valid bit from - * rx_msdu_end TLV + * hal_rx_tlv_sa_is_valid_get_be() - API to get the sa_is_valid bit from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: sa_is_valid bit */ static inline uint8_t @@ -1665,9 +1655,9 @@ hal_rx_tlv_sa_is_valid_get_be(uint8_t *buf) } /** - * hal_rx_tlv_sa_idx_get_be(): API to get the sa_idx from rx_msdu_end TLV + * hal_rx_tlv_sa_idx_get_be() - API to get the sa_idx from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: sa_idx (SA AST index) */ static inline @@ -1683,8 +1673,6 @@ uint16_t hal_rx_tlv_sa_idx_get_be(uint8_t *buf) /** * hal_rx_desc_is_first_msdu_be() - Check if first msdu - * - * @hal_soc_hdl: hal_soc handle * @hw_desc_addr: hardware descriptor address * * Return: 0 - success/ non-zero failure @@ -1698,10 +1686,10 @@ static inline uint32_t hal_rx_desc_is_first_msdu_be(void *hw_desc_addr) } /** - * hal_rx_tlv_l3_hdr_padding_get_be(): API to get the l3_header padding + * hal_rx_tlv_l3_hdr_padding_get_be() - API to get the l3_header padding * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: number of l3 header padding bytes */ static inline uint32_t hal_rx_tlv_l3_hdr_padding_get_be(uint8_t *buf) @@ -1714,11 +1702,11 @@ static inline uint32_t hal_rx_tlv_l3_hdr_padding_get_be(uint8_t *buf) return l3_header_padding; } -/* - * @ hal_rx_encryption_info_valid_be: Returns encryption type. +/** + * hal_rx_encryption_info_valid_be() - Returns encryption type. + * @buf: rx_tlv_hdr of the received packet * - * @ buf: rx_tlv_hdr of the received packet - * @ Return: encryption type + * Return: encryption type */ static inline uint32_t hal_rx_encryption_info_valid_be(uint8_t *buf) { @@ -1730,10 +1718,10 @@ static inline uint32_t hal_rx_encryption_info_valid_be(uint8_t *buf) } /** - * hal_rx_tlv_first_msdu_get_be: API to get first msdu status - * from rx_msdu_end TLV + * hal_rx_tlv_first_msdu_get_be() - API to get first msdu status from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: first_msdu */ static inline uint8_t hal_rx_tlv_first_msdu_get_be(uint8_t *buf) @@ -1747,10 +1735,10 @@ static inline uint8_t hal_rx_tlv_first_msdu_get_be(uint8_t *buf) } /** - * hal_rx_tlv_da_is_valid_get_be: API to check if da is valid - * from rx_msdu_end TLV + * hal_rx_tlv_da_is_valid_get_be() - API to check if da is valid from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: da_is_valid */ static inline uint8_t hal_rx_tlv_da_is_valid_get_be(uint8_t *buf) @@ -1764,10 +1752,10 @@ static inline uint8_t hal_rx_tlv_da_is_valid_get_be(uint8_t *buf) } /** - * hal_rx_tlv_last_msdu_get_be: API to get last msdu status - * from rx_msdu_end TLV + * hal_rx_tlv_last_msdu_get_be() - API to get last msdu status from + * rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers * - * @ buf: pointer to the start of RX PKT TLV headers * Return: last_msdu */ static inline uint8_t hal_rx_tlv_last_msdu_get_be(uint8_t *buf) @@ -1780,11 +1768,11 @@ static inline uint8_t hal_rx_tlv_last_msdu_get_be(uint8_t *buf) return last_msdu; } -/* - * hal_rx_get_mpdu_mac_ad4_valid_be(): Retrieves if mpdu 4th addr is valid +/** + * hal_rx_get_mpdu_mac_ad4_valid_be() - Retrieves if mpdu 4th addr is valid + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: value of mpdu 4th address valid field + * Return: value of mpdu 4th address valid field */ static inline bool hal_rx_get_mpdu_mac_ad4_valid_be(uint8_t *buf) { @@ -1797,7 +1785,7 @@ static inline bool hal_rx_get_mpdu_mac_ad4_valid_be(uint8_t *buf) } /** - * hal_rx_mpdu_start_sw_peer_id_get_be: Retrieve sw peer_id + * hal_rx_mpdu_start_sw_peer_id_get_be() - Retrieve sw peer_id * @buf: network buffer * * Return: sw peer_id @@ -1810,8 +1798,8 @@ static inline uint32_t hal_rx_mpdu_start_sw_peer_id_get_be(uint8_t *buf) } /** - * hal_rx_mpdu_get_to_ds_be(): API to get the tods info - * from rx_mpdu_start + * hal_rx_mpdu_get_to_ds_be() - API to get the tods info + * from rx_mpdu_start * * @buf: pointer to the start of RX PKT TLV header * Return: uint32_t(to_ds) @@ -1823,11 +1811,11 @@ static inline uint32_t hal_rx_mpdu_get_to_ds_be(uint8_t *buf) return HAL_RX_TLV_MPDU_GET_TODS(rx_pkt_tlvs); } -/* - * hal_rx_mpdu_get_fr_ds_be(): API to get the from ds info - * from rx_mpdu_start - * +/** + * hal_rx_mpdu_get_fr_ds_be() - API to get the from ds info + * from rx_mpdu_start * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(fr_ds) */ static inline uint32_t hal_rx_mpdu_get_fr_ds_be(uint8_t *buf) @@ -1837,12 +1825,12 @@ static inline uint32_t hal_rx_mpdu_get_fr_ds_be(uint8_t *buf) return HAL_RX_TLV_MPDU_GET_FROMDS(rx_pkt_tlvs); } -/* - * hal_rx_get_mpdu_frame_control_valid_be(): Retrieves mpdu - * frame control valid +/** + * hal_rx_get_mpdu_frame_control_valid_be() - Retrieves mpdu frame + * control valid + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: value of frame control valid field + * Return: value of frame control valid field */ static inline uint8_t hal_rx_get_mpdu_frame_control_valid_be(uint8_t *buf) { @@ -1851,12 +1839,12 @@ static inline uint8_t hal_rx_get_mpdu_frame_control_valid_be(uint8_t *buf) return HAL_RX_TLV_MPDU_GET_FRAME_CONTROL_VALID(rx_pkt_tlvs); } -/* - * hal_rx_mpdu_get_addr2_be(): API to check get address2 of the mpdu - * in the packet - * +/** + * hal_rx_mpdu_get_addr2_be() - API to check get address2 of the mpdu + * in the packet * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address + * * Return: success/failure */ static inline QDF_STATUS hal_rx_mpdu_get_addr2_be(uint8_t *buf, @@ -1881,12 +1869,12 @@ static inline QDF_STATUS hal_rx_mpdu_get_addr2_be(uint8_t *buf, return QDF_STATUS_E_FAILURE; } -/* - * hal_rx_mpdu_get_addr3_be(): API to get address3 of the mpdu - * in the packet - * +/** + * hal_rx_mpdu_get_addr3_be() - API to get address3 of the mpdu in the + * packet * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address + * * Return: success/failure */ static inline QDF_STATUS hal_rx_mpdu_get_addr3_be(uint8_t *buf, @@ -1911,12 +1899,12 @@ static inline QDF_STATUS hal_rx_mpdu_get_addr3_be(uint8_t *buf, return QDF_STATUS_E_FAILURE; } -/* - * hal_rx_get_mpdu_sequence_control_valid_be(): Get mpdu - * sequence control valid +/** + * hal_rx_get_mpdu_sequence_control_valid_be() - Get mpdu sequence + * control valid + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: value of sequence control valid field + * Return: value of sequence control valid field */ static inline uint8_t hal_rx_get_mpdu_sequence_control_valid_be(uint8_t *buf) { @@ -1926,9 +1914,9 @@ static inline uint8_t hal_rx_get_mpdu_sequence_control_valid_be(uint8_t *buf) } /** - * hal_rx_tid_get_be: get tid based on qos control valid. + * hal_rx_tid_get_be() - get tid based on qos control valid. * @hal_soc_hdl: hal_soc handle - * @ buf: pointer to rx pkt TLV. + * @buf: pointer to rx pkt TLV. * * Return: tid */ @@ -1968,8 +1956,8 @@ static inline uint8_t hal_rx_get_mac_addr2_valid_be(uint8_t *buf) } /** - * hal_rx_msdu_flow_idx_get_be: API to get flow index - * from rx_msdu_end TLV + * hal_rx_msdu_flow_idx_get_be() - API to get flow index from + * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index value from MSDU END TLV @@ -1982,8 +1970,10 @@ static inline uint32_t hal_rx_msdu_flow_idx_get_be(uint8_t *buf) } /** - * hal_rx_msdu_get_reo_destination_indication_be: API to get - * reo_destination_indication from rx_msdu_end TLV + * hal_rx_msdu_get_reo_destination_indication_be() - API to get + * reo_destination_indication + * from rx_msdu_end + * TLV * @buf: pointer to the start of RX PKT TLV headers * @reo_destination_indication: pointer to return value of * reo_destination_indication @@ -2000,8 +1990,8 @@ hal_rx_msdu_get_reo_destination_indication_be(uint8_t *buf, } /** - * hal_rx_msdu_flow_idx_invalid_be: API to get flow index invalid - * from rx_msdu_end TLV + * hal_rx_msdu_flow_idx_invalid_be() - API to get flow index invalid + * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index invalid value from MSDU END TLV @@ -2014,8 +2004,8 @@ static inline bool hal_rx_msdu_flow_idx_invalid_be(uint8_t *buf) } /** - * hal_rx_msdu_flow_idx_timeout_be: API to get flow index timeout - * from rx_msdu_end TLV + * hal_rx_msdu_flow_idx_timeout_be() - API to get flow index timeout + * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index timeout value from MSDU END TLV @@ -2028,8 +2018,8 @@ static inline bool hal_rx_msdu_flow_idx_timeout_be(uint8_t *buf) } /** - * hal_rx_msdu_fse_metadata_get_be: API to get FSE metadata - * from rx_msdu_end TLV + * hal_rx_msdu_fse_metadata_get_be() - API to get FSE metadata from + * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: fse metadata value from MSDU END TLV @@ -2042,8 +2032,8 @@ static inline uint32_t hal_rx_msdu_fse_metadata_get_be(uint8_t *buf) } /** - * hal_rx_msdu_cce_metadata_get_be: API to get CCE metadata - * from rx_msdu_end TLV + * hal_rx_msdu_cce_metadata_get_be() - API to get CCE metadata from + * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: cce_metadata @@ -2057,8 +2047,9 @@ hal_rx_msdu_cce_metadata_get_be(uint8_t *buf) } /** - * hal_rx_msdu_get_flow_params_be: API to get flow index, flow index invalid - * and flow index timeout from rx_msdu_end TLV + * hal_rx_msdu_get_flow_params_be() - API to get flow index, flow + * index invalid and flow index + * timeout from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * @flow_invalid: pointer to return value of flow_idx_valid * @flow_timeout: pointer to return value of flow_idx_timeout @@ -2094,10 +2085,10 @@ hal_rx_tlv_get_tcp_chksum_be(uint8_t *buf) } /** - * hal_rx_get_rx_sequence_be(): Function to retrieve rx sequence number + * hal_rx_get_rx_sequence_be() - Function to retrieve rx sequence number + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: rx sequence number + * Return: rx sequence number */ static inline uint16_t hal_rx_get_rx_sequence_be(uint8_t *buf) @@ -2227,7 +2218,7 @@ static inline uint8_t hal_rx_mpdu_start_tlv_tag_valid_be(void *rx_tlv_hdr) } /** - * hal_rx_msdu_end_offset_get_generic(): API to get the + * hal_rx_msdu_end_offset_get_generic() - API to get the * msdu_end structure offset rx_pkt_tlv structure * * NOTE: API returns offset of msdu_end TLV from structure @@ -2239,7 +2230,7 @@ static inline uint32_t hal_rx_msdu_end_offset_get_generic(void) } /** - * hal_rx_mpdu_start_offset_get_generic(): API to get the + * hal_rx_mpdu_start_offset_get_generic() - API to get the * mpdu_start structure offset rx_pkt_tlv structure * * NOTE: API returns offset of attn TLV from structure @@ -2262,7 +2253,7 @@ static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void) #define MSDU_END_WMASK 0x13FC1 /** - * hal_rx_mpdu_start_wmask_get_be(): API to get the mpdu_start_tlv word mask + * hal_rx_mpdu_start_wmask_get_be() - API to get the mpdu_start_tlv word mask * * return: Word mask for MPDU start tlv */ @@ -2272,7 +2263,7 @@ static inline uint32_t hal_rx_mpdu_start_wmask_get_be(void) } /** - * hal_rx_msdu_end_wmask_get_be(): API to get the msdu_end_tlv word mask + * hal_rx_msdu_end_wmask_get_be() - API to get the msdu_end_tlv word mask * * return: Word mask for MSDU end tlv */ @@ -2333,10 +2324,10 @@ static inline int hal_rx_get_l3_l4_offsets_be(uint8_t *buf, #endif /** -* hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length -* from rx_msdu_start TLV +* hal_rx_msdu_start_msdu_len_get_be() - API to get the MSDU length from +* rx_msdu_start TLV +* @buf: pointer to the start of RX PKT TLV headers * -* @ buf: pointer to the start of RX PKT TLV headers * Return: msdu length */ static inline uint32_t hal_rx_msdu_start_msdu_len_get_be(uint8_t *buf) @@ -2350,11 +2341,10 @@ static inline uint32_t hal_rx_msdu_start_msdu_len_get_be(uint8_t *buf) } /** - * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field - * - * @nbuf: Network buffer - * Returns: rx more fragment bit + * hal_rx_get_frame_ctrl_field_be() - Function to retrieve frame control field + * @buf: Network buffer * + * Return: frame control field */ static inline uint16_t hal_rx_get_frame_ctrl_field_be(uint8_t *buf) { @@ -2366,11 +2356,11 @@ static inline uint16_t hal_rx_get_frame_ctrl_field_be(uint8_t *buf) return frame_ctrl; } -/* - * hal_rx_tlv_get_is_decrypted_be(): API to get the decrypt status of the - * packet from msdu_end - * +/** + * hal_rx_tlv_get_is_decrypted_be() - API to get the decrypt status of + * the packet from msdu_end * @buf: pointer to the start of RX PKT TLV header + * * Return: uint32_t(decryt status) */ static inline uint32_t hal_rx_tlv_get_is_decrypted_be(uint8_t *buf) @@ -2389,7 +2379,7 @@ static inline uint32_t hal_rx_tlv_get_is_decrypted_be(uint8_t *buf) #ifdef NO_RX_PKT_HDR_TLV /** - * hal_rx_pkt_hdr_get_be(): API to get 80211 header + * hal_rx_pkt_hdr_get_be() - API to get 80211 header * @buf: start of rx_pkt_tlv * * If NO_RX_PKT_HDR_TLV is enabled, then this API assume caller gives a raw @@ -2416,7 +2406,7 @@ static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) * hal_rx_tlv_csum_err_get_be() - Get IP and tcp-udp checksum fail flag * @rx_tlv_hdr: start address of rx_tlv_hdr * @ip_csum_err: buffer to return ip_csum_fail flag - * @tcp_udp_csum_fail: placeholder to return tcp-udp checksum fail flag + * @tcp_udp_csum_err: placeholder to return tcp-udp checksum fail flag * * Return: None */ @@ -2450,10 +2440,10 @@ uint32_t hal_rx_tlv_mpdu_fcs_err_get_be(void *hw_desc_addr) } /** - * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit + * hal_rx_get_rx_more_frag_bit() - Function to retrieve more fragment bit + * @buf: Network buffer * - * @nbuf: Network buffer - * Returns: rx more fragment bit + * Return: rx more fragment bit */ static inline uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) @@ -2468,12 +2458,12 @@ uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf) return frame_ctrl; } -/* - * hal_rx_msdu_is_wlan_mcast_generic_be(): Check if the buffer is for multicast - * address +/** + * hal_rx_msdu_is_wlan_mcast_generic_be() - Check if the buffer is for + * multicast address * @nbuf: Network buffer * - * Returns: flag to indicate whether the nbuf has MC/BC address + * Return: flag to indicate whether the nbuf has MC/BC address */ static inline uint32_t hal_rx_msdu_is_wlan_mcast_generic_be(qdf_nbuf_t nbuf) { @@ -2483,9 +2473,8 @@ static inline uint32_t hal_rx_msdu_is_wlan_mcast_generic_be(qdf_nbuf_t nbuf) } /** - * hal_rx_msdu_start_msdu_len_set_be(): API to set the MSDU length - * from rx_msdu_start TLV - * + * hal_rx_msdu_start_msdu_len_set_be() - API to set the MSDU length + * from rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers * @len: msdu length * @@ -2498,8 +2487,8 @@ hal_rx_msdu_start_msdu_len_set_be(uint8_t *buf, uint32_t len) } /** - * hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(): - * Retrieve qos control valid bit from the tlv. + * hal_rx_mpdu_start_mpdu_qos_control_valid_get_be() - + * Retrieve qos control valid bit from the tlv. * @buf: pointer to rx pkt TLV. * * Return: qos control value. @@ -2513,7 +2502,7 @@ hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(uint8_t *buf) } /** - * hal_rx_msdu_end_sa_sw_peer_id_get_be(): API to get the + * hal_rx_msdu_end_sa_sw_peer_id_get_be() - API to get the * sa_sw_peer_id from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * diff --git a/hal/wifi3.0/be/hal_be_tx.h b/hal/wifi3.0/be/hal_be_tx.h index 4d1640f5df..182de04200 100644 --- a/hal/wifi3.0/be/hal_be_tx.h +++ b/hal/wifi3.0/be/hal_be_tx.h @@ -60,7 +60,8 @@ enum hal_tx_mcast_ctrl { HAL_TX_MCAST_CTRL_NO_SPECIAL, }; -/* enum hal_tx_notify_frame_type - TX notify frame type +/** + * enum hal_tx_notify_frame_type - TX notify frame type * @NO_TX_NOTIFY: Not a notify frame * @TX_HARD_NOTIFY: Hard notify TX frame * @TX_SOFT_NOTIFY_E: Soft Notify Tx frame @@ -78,7 +79,7 @@ enum hal_tx_notify_frame_type { * --------------------------------------------------------------------------- */ /** - * struct hal_tx_bank_config - SW config bank params + * union hal_tx_bank_config - SW config bank params * @epd: EPD indication flag * @encap_type: encapsulation type * @encrypt_type: encrypt type @@ -91,6 +92,8 @@ enum hal_tx_notify_frame_type { * @vdev_id_check_en: vdev id check * @pmac_id: mac id * @mcast_pkt_ctrl: mulitcast packet control + * @dscp_tid_map_id: DSCP to TID map id + * @reserved: unused bits * @val: value representing bank config */ union hal_tx_bank_config { @@ -114,14 +117,15 @@ union hal_tx_bank_config { }; /** - * struct hal_tx_cmn_config_ppe - SW config exception related parameters - * @drop_prec_err - Exception drop_prec errors. - * @fake_mac_hdr - Exception fake mac header. - * @cpu_code_inv - Exception cpu code invalid. - * @data_buff_err - Exception buffer length/offset erorors. - * @l3_l4_err - Exception m3_l4 checksum errors - * @data_offset_max - Maximum data offset allowed. - * @data_len_max - Maximum data length allowed. + * union hal_tx_cmn_config_ppe - SW config exception related parameters + * @drop_prec_err: Exception drop_prec errors. + * @fake_mac_hdr: Exception fake mac header. + * @cpu_code_inv: Exception cpu code invalid. + * @data_buff_err: Exception buffer length/offset erorors. + * @l3_l4_err: Exception m3_l4 checksum errors + * @data_offset_max: Maximum data offset allowed. + * @data_len_max: Maximum data length allowed. + * @val: aggregate 32-bit value */ union hal_tx_cmn_config_ppe { struct { @@ -137,15 +141,16 @@ union hal_tx_cmn_config_ppe { }; /** - * hal_tx_ppe_vp_config - SW config PPE VP table - * @vp_num - Virtual port number - * @pmac_id - Lmac ID + * union hal_tx_ppe_vp_config - SW config PPE VP table + * @vp_num: Virtual port number + * @pmac_id: Lmac ID * @bank_id: Bank ID corresponding to this I/F. * @vdev_id: VDEV ID of the I/F. * @search_idx_reg_num: Register number of this SI. * @use_ppe_int_pri: Use the PPE INT_PRI to TID table * @to_fw: Use FW * @drop_prec_enable: Enable precedence drop. + * @val: aggregate 32-bit value */ union hal_tx_ppe_vp_config { struct { @@ -162,9 +167,10 @@ union hal_tx_ppe_vp_config { }; /** - * hal_tx_cmn_ppe_idx_map_config: Use ppe index mapping table + * union hal_tx_ppe_idx_map_config - Use ppe index mapping table * @search_idx: Search index * @cache_set: Cache set number + * @val: aggregate 32-bit value */ union hal_tx_ppe_idx_map_config { struct { @@ -175,7 +181,7 @@ union hal_tx_ppe_idx_map_config { }; /** - * hal_tx_ppe_pri2tid_map0_config : Configure ppe INT_PRI to tid map + * union hal_tx_ppe_pri2tid_map0_config - Configure ppe INT_PRI to tid map * @int_pri0: INT_PRI_0 * @int_pri1: INT_PRI_1 * @int_pri2: INT_PRI_2 @@ -186,6 +192,7 @@ union hal_tx_ppe_idx_map_config { * @int_pri7: INT_PRI_7 * @int_pri8: INT_PRI_8 * @int_pri9: INT_PRI_9 + * @val: aggregate 32-bit value */ union hal_tx_ppe_pri2tid_map0_config { struct { @@ -204,13 +211,14 @@ union hal_tx_ppe_pri2tid_map0_config { }; /** - * hal_tx_ppe_pri2tid_map1_config : Configure ppe INT_PRI to tid map - * @int_pri0: INT_PRI_10 - * @int_pri1: INT_PRI_11 - * @int_pri2: INT_PRI_12 - * @int_pri3: INT_PRI_13 - * @int_pri4: INT_PRI_14 - * @int_pri5: INT_PRI_15 + * union hal_tx_ppe_pri2tid_map1_config - Configure ppe INT_PRI to tid map + * @int_pri10: INT_PRI_10 + * @int_pri11: INT_PRI_11 + * @int_pri12: INT_PRI_12 + * @int_pri13: INT_PRI_13 + * @int_pri14: INT_PRI_14 + * @int_pri15: INT_PRI_15 + * @val: aggregate 32-bit value */ union hal_tx_ppe_pri2tid_map1_config { struct { @@ -235,7 +243,7 @@ union hal_tx_ppe_pri2tid_map1_config { */ /** - * hal_tx_desc_set_tx_notify_frame - Set TX notify_frame field in Tx desc + * hal_tx_desc_set_tx_notify_frame() - Set TX notify_frame field in Tx desc * @desc: Handle to Tx Descriptor * @val: Value to be set * @@ -249,7 +257,7 @@ static inline void hal_tx_desc_set_tx_notify_frame(void *desc, } /** - * hal_tx_desc_set_flow_override_enable - Set flow_override_enable field + * hal_tx_desc_set_flow_override_enable() - Set flow_override_enable field * @desc: Handle to Tx Descriptor * @val: Value to be set * @@ -263,7 +271,7 @@ static inline void hal_tx_desc_set_flow_override_enable(void *desc, } /** - * hal_tx_desc_set_flow_override - Set flow_override field in TX desc + * hal_tx_desc_set_flow_override() - Set flow_override field in TX desc * @desc: Handle to Tx Descriptor * @val: Value to be set * @@ -277,7 +285,7 @@ static inline void hal_tx_desc_set_flow_override(void *desc, } /** - * hal_tx_desc_set_who_classify_info_sel - Set who_classify_info_sel field + * hal_tx_desc_set_who_classify_info_sel() - Set who_classify_info_sel field * @desc: Handle to Tx Descriptor * @val: Value to be set * @@ -291,7 +299,7 @@ static inline void hal_tx_desc_set_who_classify_info_sel(void *desc, } /** - * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor + * hal_tx_desc_set_buf_length() - Set Data length in bytes in Tx Descriptor * @desc: Handle to Tx Descriptor * @data_length: MSDU length in case of direct descriptor. * Length of link extension descriptor in case of Link extension @@ -306,7 +314,7 @@ static inline void hal_tx_desc_set_buf_length(void *desc, } /** - * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor + * hal_tx_desc_set_buf_offset() - Sets Packet Offset field in Tx descriptor * @desc: Handle to Tx Descriptor * @offset: Packet offset from Metadata in case of direct buffer descriptor. * @@ -320,8 +328,8 @@ static inline void hal_tx_desc_set_buf_offset(void *desc, } /** - * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags - * Tx Descriptor for MSDU_buffer type + * hal_tx_desc_set_l4_checksum_en() - Set TCP/IP checksum enable flags + * Tx Descriptor for MSDU_buffer type * @desc: Handle to Tx Descriptor * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) * @@ -338,10 +346,10 @@ static inline void hal_tx_desc_set_l4_checksum_en(void *desc, } /** - * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in - * Tx Descriptor for MSDU_buffer type + * hal_tx_desc_set_l3_checksum_en() - Set IPv4 checksum enable flag in + * Tx Descriptor for MSDU_buffer type * @desc: Handle to Tx Descriptor - * @checksum_en_flags: ipv4 checksum enable flags + * @en: ipv4 checksum enable flags * * Return: void */ @@ -353,8 +361,8 @@ static inline void hal_tx_desc_set_l3_checksum_en(void *desc, } /** - * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor - * @desc:Handle to Tx Descriptor + * hal_tx_desc_set_fw_metadata() - Sets the metadata that is part of TCL descriptor + * @desc: Handle to Tx Descriptor * @metadata: Metadata to be sent to Firmware * * Return: void @@ -367,8 +375,8 @@ static inline void hal_tx_desc_set_fw_metadata(void *desc, } /** - * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. - * @desc:Handle to Tx Descriptor + * hal_tx_desc_set_to_fw() - Set To_FW bit in Tx Descriptor. + * @desc: Handle to Tx Descriptor * @to_fw: if set, Forward packet to FW along with classification result * * Return: void @@ -380,8 +388,8 @@ static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) } /** - * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in - * frame) to be used for Tx Frame + * hal_tx_desc_set_hlos_tid() - Set the TID value (override DSCP/PCP fields in + * frame) to be used for Tx Frame * @desc: Handle to Tx Descriptor * @hlos_tid: HLOS TID * @@ -398,9 +406,10 @@ static inline void hal_tx_desc_set_hlos_tid(void *desc, } /** - * hal_tx_desc_sync - Commit the descriptor to Hardware - * @hal_tx_des_cached: Cached descriptor that software maintains + * hal_tx_desc_sync() - Commit the descriptor to Hardware + * @hal_tx_desc_cached: Cached descriptor that software maintains * @hw_desc: Hardware descriptor to be updated + * @num_bytes: descriptor size */ static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, void *hw_desc, uint8_t num_bytes) @@ -409,8 +418,8 @@ static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, } /** - * hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware - * @hal_tx_des_cached: Cached descriptor that software maintains + * hal_tx_desc_set_vdev_id() - set vdev id to the descriptor to Hardware + * @desc: Cached descriptor that software maintains * @vdev_id: vdev id */ static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id) @@ -420,8 +429,8 @@ static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id) } /** - * hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware - * @hal_tx_des_cached: Cached descriptor that software maintains + * hal_tx_desc_set_bank_id() - set bank id to the descriptor to Hardware + * @desc: Cached descriptor that software maintains * @bank_id: bank id */ static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id) @@ -431,9 +440,9 @@ static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id) } /** - * hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor - * to Hardware - * @hal_tx_des_cached: Cached descriptor that software maintains + * hal_tx_desc_set_tcl_cmd_type() - set tcl command type to the descriptor + * to Hardware + * @desc: Cached descriptor that software maintains * @tcl_cmd_type: tcl command type */ static inline void @@ -444,9 +453,9 @@ hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type) } /** - * hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware + * hal_tx_desc_set_lmac_id_be() - set lmac id to the descriptor to Hardware * @hal_soc_hdl: hal soc handle - * @hal_tx_des_cached: Cached descriptor that software maintains + * @desc: Cached descriptor that software maintains * @lmac_id: lmac id */ static inline void @@ -458,10 +467,10 @@ hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc, } /** - * hal_tx_desc_set_search_index_be - set search index to the - * descriptor to Hardware + * hal_tx_desc_set_search_index_be() - set search index to the + * descriptor to Hardware * @hal_soc_hdl: hal soc handle - * @hal_tx_des_cached: Cached descriptor that software maintains + * @desc: Cached descriptor that software maintains * @search_index: search index */ static inline void @@ -473,10 +482,10 @@ hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc, } /** - * hal_tx_desc_set_cache_set_num - set cache set num to the - * descriptor to Hardware + * hal_tx_desc_set_cache_set_num() - set cache set num to the + * descriptor to Hardware * @hal_soc_hdl: hal soc handle - * @hal_tx_des_cached: Cached descriptor that software maintains + * @desc: Cached descriptor that software maintains * @cache_num: cache number */ static inline void @@ -488,11 +497,11 @@ hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc, } /** - * hal_tx_desc_set_lookup_override_num - set lookup override num - * to the descriptor to Hardware + * hal_tx_desc_set_index_lookup_override() - set lookup override num to the + * descriptor to Hardware * @hal_soc_hdl: hal soc handle - * @hal_tx_des_cached: Cached descriptor that software maintains - * @cache_num: set numbernumber + * @desc: Cached descriptor that software maintains + * @num: set number */ static inline void hal_tx_desc_set_index_lookup_override(hal_soc_handle_t hal_soc_hdl, @@ -629,6 +638,7 @@ static inline uint64_t hal_tx_comp_get_desc_va(void *hal_desc) /** * hal_tx_get_num_tcl_banks() - Get number of banks for target + * @hal_soc_hdl: HAL soc handle * * Return: None */ @@ -649,8 +659,8 @@ hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl) /** * hal_tx_populate_bank_register() - populate the bank register with - * the software configs. - * @soc: HAL soc handle + * the software configs. + * @hal_soc_hdl: HAL soc handle * @config: bank config * @bank_id: bank id to be configured * @@ -679,7 +689,7 @@ hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl, /** * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id - * @hal_soc: HAL SoC context + * @hal_soc_hdl: HAL SoC context * @hal_ring_hdl: Source ring pointer * @rbm_id: return buffer manager ring id * @@ -705,13 +715,14 @@ hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, #endif /** - * hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc + * hal_tx_desc_set_buf_addr_be() - Fill Buffer Address information in Tx Desc + * @hal_soc_hdl: HAL SoC context * @desc: Handle to Tx Descriptor * @paddr: Physical Address - * @pool_id: Return Buffer Manager ID + * @rbm_id: Return Buffer Manager ID * @desc_id: Descriptor ID * @type: 0 - Address points to a MSDU buffer - * 1 - Address points to MSDU extension descriptor + * 1 - Address points to MSDU extension descriptor * * Return: void */ @@ -780,8 +791,8 @@ hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc, #endif /** - * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing - * @hal_soc: HAL SoC context + * hal_tx_vdev_mismatch_routing_set() - set vdev mismatch exception routing + * @hal_soc_hdl: HAL SoC context * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW * @@ -805,8 +816,8 @@ hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, #endif /** - * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing - * @hal_soc: HAL SoC context + * hal_tx_mcast_mlo_reinject_routing_set() - set MLO multicast reinject routing + * @hal_soc_hdl: HAL SoC context * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM * @@ -848,8 +859,8 @@ void hal_reo_config_reo2ppe_dest_info(hal_soc_handle_t hal_soc_hdl) } /** - * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table - * @hal_soc: HAL SoC Context + * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table entries + * @hal_soc_hdl: HAL SoC Context * * Return: Total number of entries. */ @@ -862,8 +873,9 @@ uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl) } /** - * hal_tx_get_num_ppe_vp_search_idx_tbl_entries() - Get the total number of search idx registers - * @hal_soc: HAL SoC Context + * hal_tx_get_num_ppe_vp_search_idx_tbl_entries() - Get the total number of + * search idx registers + * @hal_soc_hdl: HAL SoC Context * * Return: Total number of entries. */ @@ -877,7 +889,7 @@ uint32_t hal_tx_get_num_ppe_vp_search_idx_tbl_entries(hal_soc_handle_t hal_soc_h /** * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config - * @hal_soc: HAL SoC context + * @hal_soc_hdl: HAL SoC context * @cmn_cfg: HAL PPE VP common config * * Return: void @@ -892,8 +904,8 @@ hal_tx_set_ppe_cmn_cfg(hal_soc_handle_t hal_soc_hdl, } /** - * hal_tx_populate_ppe_vp_entry - Populate ppe VP entry - * @hal_soc: HAL SoC context + * hal_tx_populate_ppe_vp_entry() - Populate ppe VP entry + * @hal_soc_hdl: HAL SoC context * @vp_cfg: HAL PPE VP config * @ppe_vp_idx: PPE VP index * @@ -910,8 +922,8 @@ hal_tx_populate_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl, } /** - * hal_ppeds_cfg_ast_override_map_reg - Set ppe index mapping table value - * @hal_soc: HAL SoC context + * hal_ppeds_cfg_ast_override_map_reg() - Set ppe index mapping table value + * @hal_soc_hdl: HAL SoC context * @reg_idx: index into the table * @overide_map: HAL PPE INDEX MAPPING config * @@ -930,9 +942,10 @@ hal_ppeds_cfg_ast_override_map_reg(hal_soc_handle_t hal_soc_hdl, } /** - * hal_tx_set_int_pri2id - Set the prit2tid table. - * @hal_soc: HAL SoC context - * @pri2tid: Reference to SW INT_PRI to TID table + * hal_tx_set_int_pri2tid() - Set the pri2tid table. + * @hal_soc_hdl: HAL SoC context + * @val: value to set + * @map_no: index in SW INT_PRI to TID table * * Return: void */ @@ -946,8 +959,8 @@ hal_tx_set_int_pri2tid(hal_soc_handle_t hal_soc_hdl, } /** - * hal_tx_update_int_pri2id - Populate the prit2tid table. - * @hal_soc: HAL SoC context + * hal_tx_update_int_pri2tid() - Populate the pri2tid table. + * @hal_soc_hdl: HAL SoC context * @pri: INT_PRI value * @tid: Wi-Fi TID * @@ -963,7 +976,7 @@ hal_tx_update_int_pri2tid(hal_soc_handle_t hal_soc_hdl, } /** - * hal_tx_dump_ppe_vp_entry - Dump the PPE VP entry + * hal_tx_dump_ppe_vp_entry() - Dump the PPE VP entry * @hal_soc_hdl: HAL SoC context * * Return: void @@ -977,9 +990,10 @@ hal_tx_dump_ppe_vp_entry(hal_soc_handle_t hal_soc_hdl) } /** - * hal_tx_enable_pri2tid_map- Enable the priority to tid mapping + * hal_tx_enable_pri2tid_map() - Enable the priority to tid mapping * @hal_soc_hdl: HAL SoC context * @val: True/False value + * @ppe_vp_idx: map index * * Return: void */