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@@ -5070,12 +5070,16 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
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sde_cfg->sui_block_xin_mask = 0x261;
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sde_cfg->has_sui_blendstage = true;
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sde_cfg->has_3d_merge_reset = true;
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+ sde_cfg->has_hdr = true;
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+ sde_cfg->has_hdr_plus = true;
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+ set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
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sde_cfg->has_vig_p010 = true;
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sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;
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sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_1;
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sde_cfg->vbif_disable_inner_outer_shareable = true;
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sde_cfg->dither_luma_mode_support = true;
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sde_cfg->mdss_hw_block_size = 0x158;
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+ sde_cfg->rc_lm_flush_override = false;
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} else {
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SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
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sde_cfg->perf.min_prefill_lines = 0xffff;
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