disp: msm: sde: ctl hw flush ops clean up
Using individual flush functions for each active hw blk is not scable-able for future use. Clean up the ops to merge all flush functions into one and manage HW block id with same API. Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This commit is contained in:
Nilaan Gunabalachandran
@@ -229,6 +229,43 @@ sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
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#define PERIPH_IDX 30
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#define INTF_IDX 31
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/* struct ctl_hw_flush_cfg: Defines the active ctl hw flush config,
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* See enum ctl_hw_flush_type for types
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* @blk_max: Maximum hw idx
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* @flush_reg: Register with corresponding active ctl hw
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* @flush_idx: Corresponding index in ctl flush
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* @flush_mask_idx: Index of hw flush mask to use
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* @flush_tbl: Pointer to flush table
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*/
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struct ctl_hw_flush_cfg {
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u32 blk_max;
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u32 flush_reg;
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u32 flush_idx;
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u32 flush_mask_idx;
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const u32 *flush_tbl;
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};
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static const struct ctl_hw_flush_cfg
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ctl_hw_flush_cfg_tbl_v1[SDE_HW_FLUSH_MAX] = {
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{WB_MAX, CTL_WB_FLUSH, WB_IDX, SDE_HW_FLUSH_WB,
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wb_flush_tbl}, /* SDE_HW_FLUSH_WB */
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{DSC_MAX, CTL_DSC_FLUSH, DSC_IDX, SDE_HW_FLUSH_DSC,
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dsc_flush_tbl}, /* SDE_HW_FLUSH_DSC */
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/* VDC is flushed to dsc, flush_reg = 0 so flush is done only once */
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{VDC_MAX, 0, DSC_IDX, SDE_HW_FLUSH_DSC,
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vdc_flush_tbl}, /* SDE_HW_FLUSH_VDC */
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{MERGE_3D_MAX, CTL_MERGE_3D_FLUSH, MERGE_3D_IDX, SDE_HW_FLUSH_MERGE_3D,
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merge_3d_tbl}, /* SDE_HW_FLUSH_MERGE_3D */
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{CDM_MAX, CTL_CDM_FLUSH, CDM_IDX, SDE_HW_FLUSH_CDM,
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cdm_flush_tbl}, /* SDE_HW_FLUSH_CDM */
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{CWB_MAX, CTL_CWB_FLUSH, CWB_IDX, SDE_HW_FLUSH_CWB,
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cwb_flush_tbl}, /* SDE_HW_FLUSH_CWB */
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{INTF_MAX, CTL_PERIPH_FLUSH, PERIPH_IDX, SDE_HW_FLUSH_PERIPH,
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intf_flush_tbl }, /* SDE_HW_FLUSH_PERIPH */
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{INTF_MAX, CTL_INTF_FLUSH, INTF_IDX, SDE_HW_FLUSH_INTF,
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intf_flush_tbl } /* SDE_HW_FLUSH_INTF */
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};
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static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
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struct sde_mdss_cfg *m,
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void __iomem *addr,
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@@ -485,162 +522,54 @@ static inline int sde_hw_ctl_update_bitmask_intf(struct sde_hw_ctl *ctx,
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_wb_v1(struct sde_hw_ctl *ctx,
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enum sde_wb wb, bool enable)
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static inline int sde_hw_ctl_update_bitmask(struct sde_hw_ctl *ctx,
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enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
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{
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int ret = 0;
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if (!ctx)
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return -EINVAL;
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if (wb != WB_2) {
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SDE_ERROR("Unsupported wb %d\n", wb);
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return -EINVAL;
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switch (type) {
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case SDE_HW_FLUSH_CDM:
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ret = sde_hw_ctl_update_bitmask_cdm(ctx, blk_idx, enable);
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break;
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case SDE_HW_FLUSH_WB:
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ret = sde_hw_ctl_update_bitmask_wb(ctx, blk_idx, enable);
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break;
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case SDE_HW_FLUSH_INTF:
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ret = sde_hw_ctl_update_bitmask_intf(ctx, blk_idx, enable);
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break;
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default:
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break;
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}
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UPDATE_MASK(ctx->flush.pending_wb_flush_mask, wb_flush_tbl[wb], enable);
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if (ctx->flush.pending_wb_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 0);
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return 0;
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return ret;
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}
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static inline int sde_hw_ctl_update_bitmask_intf_v1(struct sde_hw_ctl *ctx,
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enum sde_intf intf, bool enable)
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static inline int sde_hw_ctl_update_bitmask_v1(struct sde_hw_ctl *ctx,
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enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
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{
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if (!ctx)
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const struct ctl_hw_flush_cfg *cfg;
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if (!ctx || !(type < SDE_HW_FLUSH_MAX))
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return -EINVAL;
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if (!(intf > SDE_NONE) || !(intf < INTF_MAX)) {
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SDE_ERROR("Unsupported intf %d\n", intf);
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cfg = &ctl_hw_flush_cfg_tbl_v1[type];
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if ((blk_idx <= SDE_NONE) || (blk_idx >= cfg->blk_max)) {
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SDE_ERROR("Unsupported hw idx, type:%d, blk_idx:%d, blk_max:%d",
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type, blk_idx, cfg->blk_max);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_intf_flush_mask, intf_flush_tbl[intf],
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enable);
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if (ctx->flush.pending_intf_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
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UPDATE_MASK(ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx],
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cfg->flush_tbl[blk_idx], enable);
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if (ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx])
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UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 0);
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return 0;
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}
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UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 0);
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static inline int sde_hw_ctl_update_bitmask_periph_v1(struct sde_hw_ctl *ctx,
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enum sde_intf intf, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if (!(intf > SDE_NONE) || !(intf < INTF_MAX)) {
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SDE_ERROR("Unsupported intf %d\n", intf);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_periph_flush_mask, intf_flush_tbl[intf],
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enable);
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if (ctx->flush.pending_periph_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, PERIPH_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, PERIPH_IDX, 0);
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_dsc_v1(struct sde_hw_ctl *ctx,
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enum sde_dsc dsc, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if (!(dsc > SDE_NONE) || !(dsc < DSC_MAX)) {
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SDE_ERROR("Unsupported dsc %d\n", dsc);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_dsc_flush_mask, dsc_flush_tbl[dsc],
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enable);
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if (ctx->flush.pending_dsc_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 0);
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_vdc(struct sde_hw_ctl *ctx,
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enum sde_vdc vdc, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if (!(vdc > SDE_NONE) || !(vdc < VDC_MAX)) {
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SDE_ERROR("Unsupported vdc %d\n", vdc);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_dsc_flush_mask, vdc_flush_tbl[vdc],
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enable);
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if (ctx->flush.pending_dsc_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, DSC_IDX, 0);
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_merge3d_v1(struct sde_hw_ctl *ctx,
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enum sde_merge_3d merge_3d, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if (!(merge_3d > SDE_NONE) || !(merge_3d < MERGE_3D_MAX)) {
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SDE_ERROR("Unsupported merge_3d %d\n", merge_3d);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_merge_3d_flush_mask,
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merge_3d_tbl[merge_3d], enable);
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if (ctx->flush.pending_merge_3d_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 0);
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_cdm_v1(struct sde_hw_ctl *ctx,
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enum sde_cdm cdm, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if (cdm != CDM_0) {
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SDE_ERROR("Unsupported cdm %d\n", cdm);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_cdm_flush_mask, cdm_flush_tbl[cdm],
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enable);
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if (ctx->flush.pending_cdm_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, CDM_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, CDM_IDX, 0);
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return 0;
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}
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static inline int sde_hw_ctl_update_bitmask_cwb_v1(struct sde_hw_ctl *ctx,
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enum sde_cwb cwb, bool enable)
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{
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if (!ctx)
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return -EINVAL;
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if ((cwb < CWB_1) || (cwb >= CWB_MAX)) {
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SDE_ERROR("Unsupported cwb %d\n", cwb);
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return -EINVAL;
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}
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UPDATE_MASK(ctx->flush.pending_cwb_flush_mask, cwb_flush_tbl[cwb],
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enable);
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if (ctx->flush.pending_cwb_flush_mask)
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UPDATE_MASK(ctx->flush.pending_flush_mask, CWB_IDX, 1);
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else
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UPDATE_MASK(ctx->flush.pending_flush_mask, CWB_IDX, 0);
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return 0;
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}
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@@ -648,24 +577,21 @@ static inline int sde_hw_ctl_update_pending_flush_v1(
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struct sde_hw_ctl *ctx,
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struct sde_ctl_flush_cfg *cfg)
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{
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int i;
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int i = 0;
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if (!ctx || !cfg)
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return -EINVAL;
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ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
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ctx->flush.pending_intf_flush_mask |= cfg->pending_intf_flush_mask;
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ctx->flush.pending_cdm_flush_mask |= cfg->pending_cdm_flush_mask;
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ctx->flush.pending_wb_flush_mask |= cfg->pending_wb_flush_mask;
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ctx->flush.pending_dsc_flush_mask |= cfg->pending_dsc_flush_mask;
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ctx->flush.pending_merge_3d_flush_mask |=
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cfg->pending_merge_3d_flush_mask;
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ctx->flush.pending_cwb_flush_mask |= cfg->pending_cwb_flush_mask;
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ctx->flush.pending_periph_flush_mask |= cfg->pending_periph_flush_mask;
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for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
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ctx->flush.pending_hw_flush_mask[i] |=
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cfg->pending_hw_flush_mask[i];
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for (i = 0; i < CTL_MAX_DSPP_COUNT; i++)
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ctx->flush.pending_dspp_flush_masks[i] |=
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cfg->pending_dspp_flush_masks[i];
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ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
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return 0;
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}
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@@ -708,34 +634,26 @@ static inline void _sde_hw_ctl_write_dspp_flushes(struct sde_hw_ctl *ctx) {
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static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
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{
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int i = 0;
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const struct ctl_hw_flush_cfg *cfg = &ctl_hw_flush_cfg_tbl_v1[0];
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if (!ctx)
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return -EINVAL;
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if (ctx->flush.pending_flush_mask & BIT(WB_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_WB_FLUSH,
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ctx->flush.pending_wb_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(DSC_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH,
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ctx->flush.pending_dsc_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(MERGE_3D_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
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ctx->flush.pending_merge_3d_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(CDM_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH,
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ctx->flush.pending_cdm_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(CWB_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH,
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ctx->flush.pending_cwb_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(INTF_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
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ctx->flush.pending_intf_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(PERIPH_IDX))
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SDE_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH,
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ctx->flush.pending_periph_flush_mask);
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if (ctx->flush.pending_flush_mask & BIT(DSPP_IDX))
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_sde_hw_ctl_write_dspp_flushes(ctx);
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for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
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if (cfg[i].flush_reg &&
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ctx->flush.pending_flush_mask &
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BIT(cfg[i].flush_idx))
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SDE_REG_WRITE(&ctx->hw,
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cfg[i].flush_reg,
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ctx->flush.pending_hw_flush_mask[i]);
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SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
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return 0;
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}
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@@ -1165,9 +1083,9 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
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if (merge_3d_idx) {
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/* disable and flush merge3d_blk */
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ctx->flush.pending_merge_3d_flush_mask =
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BIT(merge_3d_idx - MERGE_3D_0);
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merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
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ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_MERGE_3D] =
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BIT(merge_3d_idx - MERGE_3D_0);
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UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
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SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
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}
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@@ -1175,16 +1093,18 @@ static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
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sde_hw_ctl_clear_all_blendstages(ctx);
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if (cfg->intf_count) {
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ctx->flush.pending_intf_flush_mask = intf_flush;
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ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_INTF] =
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intf_flush;
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UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
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SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
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}
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if (cfg->wb_count) {
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ctx->flush.pending_wb_flush_mask = wb_flush;
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ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] = wb_flush;
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UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
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SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
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}
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return 0;
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}
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@@ -1401,17 +1321,9 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
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ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
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ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
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ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm_v1;
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ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb_v1;
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ops->update_bitmask_intf = sde_hw_ctl_update_bitmask_intf_v1;
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ops->update_bitmask_dsc = sde_hw_ctl_update_bitmask_dsc_v1;
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ops->update_bitmask_vdc = sde_hw_ctl_update_bitmask_vdc;
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ops->update_bitmask_merge3d =
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sde_hw_ctl_update_bitmask_merge3d_v1;
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ops->update_bitmask_cwb = sde_hw_ctl_update_bitmask_cwb_v1;
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ops->update_bitmask_periph =
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sde_hw_ctl_update_bitmask_periph_v1;
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ops->update_bitmask = sde_hw_ctl_update_bitmask_v1;
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ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
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ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
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ops->get_scheduler_status = sde_hw_ctl_get_scheduler_status;
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ops->read_active_status = sde_hw_ctl_read_active_status;
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@@ -1421,9 +1333,7 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
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ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
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ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm;
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ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb;
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ops->update_bitmask_intf = sde_hw_ctl_update_bitmask_intf;
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ops->update_bitmask = sde_hw_ctl_update_bitmask;
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ops->get_ctl_intf = sde_hw_ctl_get_intf;
|
||||
}
|
||||
ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
|
||||
|
||||
Reference in New Issue
Block a user