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disp: msm: sde: ctl hw flush ops clean up

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Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.

Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This commit is contained in:
Nilaan Gunabalachandran
2019-11-12 09:47:26 -05:00
parent 664e64b84b
commit f51424f8a7
7 changed files with 194 additions and 320 deletions
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33
msm/sde/sde_encoder.c
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@@ -2731,9 +2731,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
false, phys_enc->hw_pp->idx);
if (phys_enc->hw_ctl->ops.update_bitmask_wb)
phys_enc->hw_ctl->ops.update_bitmask_wb(
if (phys_enc->hw_ctl->ops.update_bitmask)
phys_enc->hw_ctl->ops.update_bitmask(
phys_enc->hw_ctl,
SDE_HW_FLUSH_WB,
wb_enc->hw_wb->idx, true);
}
} else {
@@ -2742,9 +2743,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
phys_enc->hw_intf, false,
phys_enc->hw_pp->idx);
if (phys_enc->hw_ctl->ops.update_bitmask_intf)
phys_enc->hw_ctl->ops.update_bitmask_intf(
if (phys_enc->hw_ctl->ops.update_bitmask)
phys_enc->hw_ctl->ops.update_bitmask(
phys_enc->hw_ctl,
SDE_HW_FLUSH_INTF,
phys_enc->hw_intf->idx, true);
}
}
@@ -2752,10 +2754,10 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
if (phys_enc->hw_ctl->ops.update_bitmask_merge3d &&
if (phys_enc->hw_ctl->ops.update_bitmask &&
phys_enc->hw_pp->merge_3d)
phys_enc->hw_ctl->ops.update_bitmask_merge3d(
phys_enc->hw_ctl,
phys_enc->hw_ctl->ops.update_bitmask(
phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
phys_enc->hw_pp->merge_3d->idx, true);
}
@@ -2764,9 +2766,9 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
false, phys_enc->hw_pp->idx);
if (phys_enc->hw_ctl->ops.update_bitmask_cdm)
phys_enc->hw_ctl->ops.update_bitmask_cdm(
phys_enc->hw_ctl,
if (phys_enc->hw_ctl->ops.update_bitmask)
phys_enc->hw_ctl->ops.update_bitmask(
phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
phys_enc->hw_cdm->idx, true);
}
@@ -3112,18 +3114,18 @@ static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
ctl->ops.update_bitmask_periph) {
ctl->ops.update_bitmask) {
/* perform peripheral flush on every frame update for dp dsc */
if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
phys->comp_ratio && c_conn->ops.update_pps) {
c_conn->ops.update_pps(phys->connector, NULL,
c_conn->display);
ctl->ops.update_bitmask_periph(ctl,
ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
phys->hw_intf->idx, 1);
}
if (sde_enc->dynamic_hdr_updated)
ctl->ops.update_bitmask_periph(ctl,
ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
phys->hw_intf->idx, 1);
}
@@ -3816,9 +3818,10 @@ static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
if (!hw_intf)
continue;
if (phys_enc->hw_ctl->ops.update_bitmask_intf)
phys_enc->hw_ctl->ops.update_bitmask_intf(
if (phys_enc->hw_ctl->ops.update_bitmask)
phys_enc->hw_ctl->ops.update_bitmask(
phys_enc->hw_ctl,
SDE_HW_FLUSH_INTF,
hw_intf->idx, 1);
intf_valid = true;