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@@ -207,6 +207,7 @@ static void _sde_encoder_phys_signal_frame_done(struct sde_encoder_phys *phys_en
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struct sde_encoder_phys_cmd *cmd_enc;
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struct sde_encoder_phys_cmd *cmd_enc;
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struct sde_hw_ctl *ctl;
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struct sde_hw_ctl *ctl;
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u32 scheduler_status = INVALID_CTL_STATUS, event = 0;
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u32 scheduler_status = INVALID_CTL_STATUS, event = 0;
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+ struct sde_hw_pp_vsync_info info[MAX_CHANNELS_PER_ENC] = {{0}};
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cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
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cmd_enc = to_sde_encoder_phys_cmd(phys_enc);
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ctl = phys_enc->hw_ctl;
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ctl = phys_enc->hw_ctl;
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@@ -230,9 +231,12 @@ static void _sde_encoder_phys_signal_frame_done(struct sde_encoder_phys *phys_en
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if (ctl->ops.get_scheduler_status)
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if (ctl->ops.get_scheduler_status)
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scheduler_status = ctl->ops.get_scheduler_status(ctl);
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scheduler_status = ctl->ops.get_scheduler_status(ctl);
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- SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0,
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- phys_enc->hw_pp->idx - PINGPONG_0, event, scheduler_status,
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- phys_enc->autorefresh_disable_trans);
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+ sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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+ SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, phys_enc->hw_pp->idx - PINGPONG_0,
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+ event, scheduler_status, phys_enc->autorefresh_disable_trans, info[0].pp_idx,
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+ info[0].intf_idx, info[0].intf_frame_count, info[0].wr_ptr_line_count,
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+ info[0].rd_ptr_line_count, info[1].pp_idx, info[1].intf_idx,
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+ info[1].intf_frame_count, info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
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/*
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/*
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* For hw-fences, in the last frame during the autorefresh disable transition
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* For hw-fences, in the last frame during the autorefresh disable transition
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@@ -338,12 +342,10 @@ static void sde_encoder_phys_cmd_te_rd_ptr_irq(void *arg, int irq_idx)
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fence_ready = ctl->ops.get_hw_fence_status(ctl);
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fence_ready = ctl->ops.get_hw_fence_status(ctl);
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sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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- SDE_EVT32_IRQ(DRMID(phys_enc->parent),
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- info[0].pp_idx, info[0].intf_idx,
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- info[0].wr_ptr_line_count, info[0].intf_frame_count, info[0].rd_ptr_line_count,
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- info[1].pp_idx, info[1].intf_idx,
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- info[1].wr_ptr_line_count, info[1].intf_frame_count, info[1].rd_ptr_line_count,
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- scheduler_status, fence_ready);
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+ SDE_EVT32_IRQ(DRMID(phys_enc->parent), scheduler_status, fence_ready, info[0].pp_idx,
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+ info[0].intf_idx, info[0].intf_frame_count, info[0].wr_ptr_line_count,
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+ info[0].rd_ptr_line_count, info[1].pp_idx, info[1].intf_idx,
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+ info[1].intf_frame_count, info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
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if (phys_enc->parent_ops.handle_vblank_virt)
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if (phys_enc->parent_ops.handle_vblank_virt)
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phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
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phys_enc->parent_ops.handle_vblank_virt(phys_enc->parent,
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@@ -379,10 +381,11 @@ static void sde_encoder_phys_cmd_wr_ptr_irq(void *arg, int irq_idx)
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}
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}
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sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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- SDE_EVT32_IRQ(DRMID(phys_enc->parent),
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- ctl->idx - CTL_0, event,
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- info[0].pp_idx, info[0].intf_idx, info[0].wr_ptr_line_count,
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- info[1].pp_idx, info[1].intf_idx, info[1].wr_ptr_line_count, qsync_mode);
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+ SDE_EVT32_IRQ(DRMID(phys_enc->parent), ctl->idx - CTL_0, event, qsync_mode,
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+ info[0].pp_idx, info[0].intf_idx, info[0].intf_frame_count,
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+ info[0].wr_ptr_line_count, info[0].rd_ptr_line_count, info[1].pp_idx,
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+ info[1].intf_idx, info[1].intf_frame_count, info[1].wr_ptr_line_count,
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+ info[1].rd_ptr_line_count);
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if (qsync_mode &&
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if (qsync_mode &&
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!test_bit(SDE_INTF_TE_SINGLE_UPDATE, &phys_enc->hw_intf->cap->features))
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!test_bit(SDE_INTF_TE_SINGLE_UPDATE, &phys_enc->hw_intf->cap->features))
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@@ -1154,6 +1157,13 @@ static void sde_encoder_phys_cmd_tearcheck_config(
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tc_cfg.sync_cfg_height,
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tc_cfg.sync_cfg_height,
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tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
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tc_cfg.sync_threshold_start, tc_cfg.sync_threshold_continue);
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+ SDE_EVT32(phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->hw_intf->idx - INTF_0,
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+ vsync_hz, mode->vtotal, vrefresh);
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+ SDE_EVT32(tc_enable, tc_cfg.start_pos, tc_cfg.rd_ptr_irq, tc_cfg.wr_ptr_irq,
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+ tc_cfg.hw_vsync_mode, tc_cfg.vsync_count, tc_cfg.vsync_init_val,
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+ tc_cfg.sync_cfg_height, tc_cfg.sync_threshold_start,
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+ tc_cfg.sync_threshold_continue);
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+
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if (phys_enc->has_intf_te) {
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if (phys_enc->has_intf_te) {
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phys_enc->hw_intf->ops.setup_tearcheck(phys_enc->hw_intf,
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phys_enc->hw_intf->ops.setup_tearcheck(phys_enc->hw_intf,
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&tc_cfg);
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&tc_cfg);
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@@ -1958,6 +1968,7 @@ static void sde_encoder_phys_cmd_trigger_start(
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struct sde_encoder_phys_cmd *cmd_enc =
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struct sde_encoder_phys_cmd *cmd_enc =
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to_sde_encoder_phys_cmd(phys_enc);
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to_sde_encoder_phys_cmd(phys_enc);
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u32 frame_cnt;
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u32 frame_cnt;
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+ struct sde_hw_pp_vsync_info info[MAX_CHANNELS_PER_ENC] = {{0}};
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if (!phys_enc)
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if (!phys_enc)
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return;
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return;
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@@ -1971,6 +1982,12 @@ static void sde_encoder_phys_cmd_trigger_start(
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sde_encoder_helper_trigger_start(phys_enc);
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sde_encoder_helper_trigger_start(phys_enc);
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}
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}
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+ sde_encoder_helper_get_pp_line_count(phys_enc->parent, info);
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+ SDE_EVT32(DRMID(phys_enc->parent), frame_cnt, info[0].pp_idx, info[0].intf_idx,
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+ info[0].intf_frame_count, info[0].wr_ptr_line_count, info[0].rd_ptr_line_count,
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+ info[1].pp_idx, info[1].intf_idx, info[1].intf_frame_count,
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+ info[1].wr_ptr_line_count, info[1].rd_ptr_line_count);
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+
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/* wr_ptr_wait_success is set true when wr_ptr arrives */
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/* wr_ptr_wait_success is set true when wr_ptr arrives */
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cmd_enc->wr_ptr_wait_success = false;
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cmd_enc->wr_ptr_wait_success = false;
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}
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}
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