qcacmn: Add fields for Tx TQM and FW exception drops
VoW stats should contain fields to count TQM and FW exception drops Change-Id: I71a81b8e9cc9428b5c727d77c0eeec5bb23a2b42
这个提交包含在:
@@ -70,6 +70,8 @@
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#define CDP_MAX_RX_RINGS 4 /* max rx rings */
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#define CDP_MAX_TX_COMP_RINGS 3 /* max tx completion rings */
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#define CDP_MAX_TX_TQM_STATUS 9 /* max tx tqm completion status */
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#define CDP_MAX_TX_HTT_STATUS 7 /* max tx htt completion status */
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/* TID level VoW stats macros
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* to add and get stats
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@@ -347,6 +349,8 @@ struct cdp_delay_stats {
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* @success_cnt: total successful transmit count
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* @comp_fail_cnt: firmware drop found in tx completion path
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* @swdrop_cnt: software drop in tx path
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* @tqm_status_cnt: TQM completion status count
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* @htt_status_cnt: HTT completion status count
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*/
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struct cdp_tid_tx_stats {
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struct cdp_delay_stats swq_delay;
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@@ -355,6 +359,8 @@ struct cdp_tid_tx_stats {
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uint64_t success_cnt;
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uint64_t comp_fail_cnt;
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uint64_t swdrop_cnt[TX_MAX_DROP];
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uint64_t tqm_status_cnt[CDP_MAX_TX_TQM_STATUS];
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uint64_t htt_status_cnt[CDP_MAX_TX_HTT_STATUS];
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};
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/*
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@@ -4097,7 +4097,7 @@ dp_accumulate_tid_stats(struct dp_pdev *pdev, uint8_t tid,
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struct cdp_tid_tx_stats *total_tx,
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struct cdp_tid_rx_stats *total_rx, uint8_t type)
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{
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uint8_t ring_id = 0, drop = 0;
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uint8_t ring_id = 0, drop = 0, tqm_status_idx = 0, htt_status_idx = 0;
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struct cdp_tid_stats *tid_stats = &pdev->stats.tid_stats;
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struct cdp_tid_tx_stats *per_ring_tx = NULL;
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struct cdp_tid_rx_stats *per_ring_rx = NULL;
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@@ -4119,7 +4119,16 @@ dp_accumulate_tid_stats(struct dp_pdev *pdev, uint8_t tid,
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for (ring_id = 0; ring_id < CDP_MAX_TX_COMP_RINGS; ring_id++) {
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per_ring_tx = &tid_stats->tid_tx_stats[ring_id][tid];
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total_tx->success_cnt += per_ring_tx->success_cnt;
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total_tx->comp_fail_cnt += per_ring_tx->comp_fail_cnt;
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for (tqm_status_idx = 0; tqm_status_idx < CDP_MAX_TX_TQM_STATUS; tqm_status_idx++) {
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total_tx->tqm_status_cnt[tqm_status_idx] +=
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per_ring_tx->tqm_status_cnt[tqm_status_idx];
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}
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for (htt_status_idx = 0; htt_status_idx < CDP_MAX_TX_HTT_STATUS; htt_status_idx++) {
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total_tx->htt_status_cnt[htt_status_idx] +=
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per_ring_tx->htt_status_cnt[htt_status_idx];
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}
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for (drop = 0; drop < TX_MAX_DROP; drop++)
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total_tx->swdrop_cnt[drop] +=
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per_ring_tx->swdrop_cnt[drop];
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@@ -4170,7 +4179,7 @@ void dp_pdev_print_tid_stats(struct dp_pdev *pdev)
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{
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struct cdp_tid_tx_stats total_tx;
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struct cdp_tid_rx_stats total_rx;
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uint8_t tid;
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uint8_t tid, tqm_status_idx, htt_status_idx;
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DP_PRINT_STATS("Packets received in hardstart: %llu ",
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pdev->stats.tid_stats.ingress_stack);
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@@ -4182,9 +4191,24 @@ void dp_pdev_print_tid_stats(struct dp_pdev *pdev)
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dp_accumulate_tid_stats(pdev, tid, &total_tx, &total_rx,
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TID_COUNTER_STATS);
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DP_PRINT_STATS("----TID: %d----", tid);
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DP_PRINT_STATS("Tx Success Count: %llu", total_tx.success_cnt);
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DP_PRINT_STATS("Tx Firmware Drop Count: %llu",
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total_tx.comp_fail_cnt);
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DP_PRINT_STATS("Tx TQM Success Count: %llu",
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total_tx.tqm_status_cnt[HAL_TX_TQM_RR_FRAME_ACKED]);
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DP_PRINT_STATS("Tx HTT Success Count: %llu",
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total_tx.htt_status_cnt[HTT_TX_FW2WBM_TX_STATUS_OK]);
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for (tqm_status_idx = 1; tqm_status_idx < CDP_MAX_TX_TQM_STATUS; tqm_status_idx++) {
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if (total_tx.tqm_status_cnt[tqm_status_idx]) {
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DP_PRINT_STATS("Tx TQM Drop Count[%d]: %llu",
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tqm_status_idx, total_tx.tqm_status_cnt[tqm_status_idx]);
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}
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}
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for (htt_status_idx = 1; htt_status_idx < CDP_MAX_TX_HTT_STATUS; htt_status_idx++) {
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if (total_tx.htt_status_cnt[htt_status_idx]) {
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DP_PRINT_STATS("Tx HTT Drop Count[%d]: %llu",
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htt_status_idx, total_tx.htt_status_cnt[htt_status_idx]);
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}
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}
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DP_PRINT_STATS("Tx Hardware Drop Count: %llu",
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total_tx.swdrop_cnt[TX_HW_ENQUEUE]);
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DP_PRINT_STATS("Tx Software Drop Count: %llu",
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@@ -2852,12 +2852,13 @@ dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
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peer->stats.tx.dropped.fw_reason2 +
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peer->stats.tx.dropped.fw_reason3;
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if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
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tid_stats->comp_fail_cnt++;
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return;
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if (ts->status < CDP_MAX_TX_TQM_STATUS) {
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tid_stats->tqm_status_cnt[ts->status]++;
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}
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tid_stats->success_cnt++;
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if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
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return;
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}
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DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
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@@ -3327,11 +3328,8 @@ void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
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if (qdf_unlikely(pdev->delay_stats_flag))
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dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
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if (qdf_unlikely(tx_status != HTT_TX_FW2WBM_TX_STATUS_OK)) {
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ts.status = HAL_TX_TQM_RR_REM_CMD_REM;
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tid_stats->comp_fail_cnt++;
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} else {
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tid_stats->success_cnt++;
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if (tx_status < CDP_MAX_TX_HTT_STATUS) {
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tid_stats->htt_status_cnt[tx_status]++;
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}
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peer = dp_peer_find_by_id(soc, ts.peer_id);
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@@ -256,6 +256,8 @@ enum hal_tx_encap_type {
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* remove reason is fw_reason2
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* @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that
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* remove reason is fw_reason3
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* @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that
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* remove reason is remove disable queue
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*/
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enum hal_tx_tqm_release_reason {
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HAL_TX_TQM_RR_FRAME_ACKED,
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@@ -266,6 +268,7 @@ enum hal_tx_tqm_release_reason {
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HAL_TX_TQM_RR_FW_REASON1,
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HAL_TX_TQM_RR_FW_REASON2,
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HAL_TX_TQM_RR_FW_REASON3,
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HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE,
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};
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/* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports
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