samsung-sm8650/android_kernel_samsung_sm8650-modules
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Kods Problēmas Izmaiņu pieprasījumi Darbības Pakotnes Projekti Laidieni Vikivietne Aktivitāte

drm/msm/dsi-staging: update dsi clock calculations

Pārlūkot izejas kodu 
Change updates dsi clock calculations for command mode
as per recommendation. Now dsi clocks are tied to
frame transer time. Propagate correct frame transfer
time to hal to update mdp clocks and bandwidth needed
accordingly.

Change-Id: I46f9038622ddd47cc53c5f3d54229f69a7008c8a
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Šī revīzija ir iekļauta:
Vara Reddy
2019-05-02 13:42:06 -07:00
vecāks 74f328561e
revīzija f28b596aac
6 mainīti faili ar 143 papildinājumiem un 19 dzēšanām
Lejupielādēt ielāpa failu Lejupielādēt izmaiņu failu Izvērst visus failus Savērst visus failus

40
msm/dsi/dsi_ctrl.c
Parādīt failu

@@ -826,18 +826,22 @@ int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format)
}
static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
struct dsi_host_config *config, void *clk_handle)
struct dsi_host_config *config, void *clk_handle,
struct dsi_display_mode *mode)
{
int rc = 0;
u32 num_of_lanes = 0;
u32 bpp, refresh_rate = TICKS_IN_MICRO_SECOND;
u32 bpp, frame_time_us;
u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
byte_clk_rate;
struct dsi_host_common_cfg *host_cfg = &config->common_config;
struct dsi_mode_info *timing = &config->video_timing;
u64 dsi_transfer_time_us = mode->priv_info->dsi_transfer_time_us;
u64 min_dsi_clk_hz = mode->priv_info->min_dsi_clk_hz;
/* Get bits per pxl in desitnation format */
/* Get bits per pxl in destination format */
bpp = dsi_ctrl_pixel_format_to_bpp(host_cfg->dst_format);
frame_time_us = mult_frac(1000, 1000, (timing->refresh_rate));
if (host_cfg->data_lanes & DSI_DATA_LANE_0)
num_of_lanes++;
@@ -848,18 +852,20 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
if (host_cfg->data_lanes & DSI_DATA_LANE_3)
num_of_lanes++;
if (config->bit_clk_rate_hz_override == 0) {
config->common_config.num_data_lanes = num_of_lanes;
config->common_config.bpp = bpp;
if (config->bit_clk_rate_hz_override != 0) {
bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
} else if (config->panel_mode == DSI_OP_CMD_MODE) {
/* Calculate the bit rate needed to match dsi transfer time */
bit_rate = mult_frac(min_dsi_clk_hz, frame_time_us,
dsi_transfer_time_us);
bit_rate = bit_rate * num_of_lanes;
} else {
h_period = DSI_H_TOTAL_DSC(timing);
v_period = DSI_V_TOTAL(timing);
if (config->panel_mode == DSI_OP_CMD_MODE)
do_div(refresh_rate, timing->mdp_transfer_time_us);
else
refresh_rate = timing->refresh_rate;
bit_rate = h_period * v_period * refresh_rate * bpp;
} else {
bit_rate = config->bit_clk_rate_hz_override * num_of_lanes;
bit_rate = h_period * v_period * timing->refresh_rate * bpp;
}
bit_rate_per_lane = bit_rate;
@@ -2865,7 +2871,8 @@ error:
*/
int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
struct dsi_host_config *config,
int flags, void *clk_handle)
struct dsi_display_mode *mode, int flags,
void *clk_handle)
{
int rc = 0;
@@ -2883,9 +2890,10 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl,
}
if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR))) {
rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle);
rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle,
mode);
if (rc) {
pr_err("[%s] failed to update link frequencies, rc=%d\n",
pr_err("[%s] failed to update link frequency, rc=%d\n",
ctrl->name, rc);
goto error;
}