From f206e6f9215f2e4c246981c4c2f1591122742ca3 Mon Sep 17 00:00:00 2001 From: Michael Ru Date: Mon, 29 Mar 2021 11:23:03 -0400 Subject: [PATCH] disp: msm: dsi: remove unsupported PHY versions Removes files and version checks for unsupported DSI PHY versions. Change-Id: I47223a3860e3bcf48eb3b74e405064d8eb375f16 Signed-off-by: Michael Ru --- msm/Kbuild | 2 - msm/dsi/dsi_catalog.c | 34 -- msm/dsi/dsi_display.c | 5 +- msm/dsi/dsi_phy.c | 48 --- msm/dsi/dsi_phy_hw.h | 8 - msm/dsi/dsi_phy_hw_v2_0.c | 636 ---------------------------------- msm/dsi/dsi_phy_timing_calc.c | 19 - msm/dsi/dsi_phy_timing_v2_0.c | 118 ------- 8 files changed, 1 insertion(+), 869 deletions(-) delete mode 100644 msm/dsi/dsi_phy_hw_v2_0.c delete mode 100644 msm/dsi/dsi_phy_timing_v2_0.c diff --git a/msm/Kbuild b/msm/Kbuild index 9dba479efb..0dab5b227f 100644 --- a/msm/Kbuild +++ b/msm/Kbuild @@ -180,11 +180,9 @@ msm_drm-$(CONFIG_DRM_SDE_RSC) += sde_rsc.o \ msm_drm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi_phy.o \ dsi/dsi_pwr.o \ dsi/dsi_phy.o \ - dsi/dsi_phy_hw_v2_0.o \ dsi/dsi_phy_hw_v3_0.o \ dsi/dsi_phy_hw_v4_0.o \ dsi/dsi_phy_timing_calc.o \ - dsi/dsi_phy_timing_v2_0.o \ dsi/dsi_phy_timing_v3_0.o \ dsi/dsi_phy_timing_v4_0.o \ dsi/dsi_pll.o \ diff --git a/msm/dsi/dsi_catalog.c b/msm/dsi/dsi_catalog.c index f692ea9cf7..0fade39ba4 100644 --- a/msm/dsi/dsi_catalog.c +++ b/msm/dsi/dsi_catalog.c @@ -153,34 +153,6 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, return rc; } -/** - * dsi_catalog_phy_2_0_init() - catalog init for DSI PHY 14nm - */ -static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy) -{ - phy->ops.regulator_enable = dsi_phy_hw_v2_0_regulator_enable; - phy->ops.regulator_disable = dsi_phy_hw_v2_0_regulator_disable; - phy->ops.enable = dsi_phy_hw_v2_0_enable; - phy->ops.disable = dsi_phy_hw_v2_0_disable; - phy->ops.calculate_timing_params = - dsi_phy_hw_calculate_timing_params; - phy->ops.phy_idle_on = dsi_phy_hw_v2_0_idle_on; - phy->ops.phy_idle_off = dsi_phy_hw_v2_0_idle_off; - phy->ops.calculate_timing_params = - dsi_phy_hw_calculate_timing_params; - phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v2_0; - phy->ops.clamp_ctrl = dsi_phy_hw_v2_0_clamp_ctrl; - phy->ops.dyn_refresh_ops.dyn_refresh_config = - dsi_phy_hw_v2_0_dyn_refresh_config; - phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay = - dsi_phy_hw_v2_0_dyn_refresh_pipe_delay; - phy->ops.dyn_refresh_ops.dyn_refresh_helper = - dsi_phy_hw_v2_0_dyn_refresh_helper; - phy->ops.dyn_refresh_ops.dyn_refresh_trigger_sel = NULL; - phy->ops.dyn_refresh_ops.cache_phy_timings = - dsi_phy_hw_v2_0_cache_phy_timings; -} - /** * dsi_catalog_phy_3_0_init() - catalog init for DSI PHY 10nm */ @@ -286,9 +258,6 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, dsi_phy_timing_calc_init(phy, version); switch (version) { - case DSI_PHY_VERSION_2_0: - dsi_catalog_phy_2_0_init(phy); - break; case DSI_PHY_VERSION_3_0: dsi_catalog_phy_3_0_init(phy); break; @@ -298,9 +267,6 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, case DSI_PHY_VERSION_4_3: dsi_catalog_phy_4_0_init(phy); break; - case DSI_PHY_VERSION_0_0_HPM: - case DSI_PHY_VERSION_0_0_LPM: - case DSI_PHY_VERSION_1_0: default: return -ENOTSUPP; } diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index 20e19732ea..f24b0e5830 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -4333,10 +4333,7 @@ void dsi_display_update_byte_intf_div(struct dsi_display *display) config = &display->panel->host_config; phy_ver = dsi_phy_get_version(m_ctrl->phy); - if (phy_ver <= DSI_PHY_VERSION_2_0) - config->byte_intf_clk_div = 1; - else - config->byte_intf_clk_div = 2; + config->byte_intf_clk_div = 2; } static int dsi_display_update_dsi_bitrate(struct dsi_display *display, diff --git a/msm/dsi/dsi_phy.c b/msm/dsi/dsi_phy.c index db454f3bc8..16a42a4162 100644 --- a/msm/dsi/dsi_phy.c +++ b/msm/dsi/dsi_phy.c @@ -31,34 +31,6 @@ struct dsi_phy_list_item { static LIST_HEAD(dsi_phy_list); static DEFINE_MUTEX(dsi_phy_list_lock); -static const struct dsi_ver_spec_info dsi_phy_v0_0_hpm = { - .version = DSI_PHY_VERSION_0_0_HPM, - .lane_cfg_count = 4, - .strength_cfg_count = 2, - .regulator_cfg_count = 1, - .timing_cfg_count = 8, -}; -static const struct dsi_ver_spec_info dsi_phy_v0_0_lpm = { - .version = DSI_PHY_VERSION_0_0_LPM, - .lane_cfg_count = 4, - .strength_cfg_count = 2, - .regulator_cfg_count = 1, - .timing_cfg_count = 8, -}; -static const struct dsi_ver_spec_info dsi_phy_v1_0 = { - .version = DSI_PHY_VERSION_1_0, - .lane_cfg_count = 4, - .strength_cfg_count = 2, - .regulator_cfg_count = 1, - .timing_cfg_count = 8, -}; -static const struct dsi_ver_spec_info dsi_phy_v2_0 = { - .version = DSI_PHY_VERSION_2_0, - .lane_cfg_count = 4, - .strength_cfg_count = 2, - .regulator_cfg_count = 1, - .timing_cfg_count = 8, -}; static const struct dsi_ver_spec_info dsi_phy_v3_0 = { .version = DSI_PHY_VERSION_3_0, .lane_cfg_count = 4, @@ -100,14 +72,6 @@ static const struct dsi_ver_spec_info dsi_phy_v4_3 = { }; static const struct of_device_id msm_dsi_phy_of_match[] = { - { .compatible = "qcom,dsi-phy-v0.0-hpm", - .data = &dsi_phy_v0_0_hpm,}, - { .compatible = "qcom,dsi-phy-v0.0-lpm", - .data = &dsi_phy_v0_0_lpm,}, - { .compatible = "qcom,dsi-phy-v1.0", - .data = &dsi_phy_v1_0,}, - { .compatible = "qcom,dsi-phy-v2.0", - .data = &dsi_phy_v2_0,}, { .compatible = "qcom,dsi-phy-v3.0", .data = &dsi_phy_v3_0,}, { .compatible = "qcom,dsi-phy-v4.0", @@ -166,18 +130,6 @@ static int dsi_phy_regmap_init(struct platform_device *pdev, DSI_PHY_DBG(phy, "map dsi_phy registers to %pK\n", phy->hw.base); - switch (phy->ver_info->version) { - case DSI_PHY_VERSION_2_0: - ptr = msm_ioremap(pdev, "phy_clamp_base", phy->name); - if (IS_ERR(ptr)) - phy->hw.phy_clamp_base = NULL; - else - phy->hw.phy_clamp_base = ptr; - break; - default: - break; - } - return rc; } diff --git a/msm/dsi/dsi_phy_hw.h b/msm/dsi/dsi_phy_hw.h index cf940e3a57..8d94fffc0a 100644 --- a/msm/dsi/dsi_phy_hw.h +++ b/msm/dsi/dsi_phy_hw.h @@ -24,10 +24,6 @@ /** * enum dsi_phy_version - DSI PHY version enumeration * @DSI_PHY_VERSION_UNKNOWN: Unknown version. - * @DSI_PHY_VERSION_0_0_HPM: 28nm-HPM. - * @DSI_PHY_VERSION_0_0_LPM: 28nm-HPM. - * @DSI_PHY_VERSION_1_0: 20nm - * @DSI_PHY_VERSION_2_0: 14nm * @DSI_PHY_VERSION_3_0: 10nm * @DSI_PHY_VERSION_4_0: 7nm * @DSI_PHY_VERSION_4_1: 7nm @@ -37,10 +33,6 @@ */ enum dsi_phy_version { DSI_PHY_VERSION_UNKNOWN, - DSI_PHY_VERSION_0_0_HPM, /* 28nm-HPM */ - DSI_PHY_VERSION_0_0_LPM, /* 28nm-LPM */ - DSI_PHY_VERSION_1_0, /* 20nm */ - DSI_PHY_VERSION_2_0, /* 14nm */ DSI_PHY_VERSION_3_0, /* 10nm */ DSI_PHY_VERSION_4_0, /* 7nm */ DSI_PHY_VERSION_4_1, /* 7nm */ diff --git a/msm/dsi/dsi_phy_hw_v2_0.c b/msm/dsi/dsi_phy_hw_v2_0.c deleted file mode 100644 index 835e2cf3f0..0000000000 --- a/msm/dsi/dsi_phy_hw_v2_0.c +++ /dev/null @@ -1,636 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. - */ - -#include -#include -#include "dsi_hw.h" -#include "dsi_phy_hw.h" - -#define DSIPHY_CMN_REVISION_ID0 0x0000 -#define DSIPHY_CMN_REVISION_ID1 0x0004 -#define DSIPHY_CMN_REVISION_ID2 0x0008 -#define DSIPHY_CMN_REVISION_ID3 0x000C -#define DSIPHY_CMN_CLK_CFG0 0x0010 -#define DSIPHY_CMN_CLK_CFG1 0x0014 -#define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018 -#define DSIPHY_CMN_CTRL_0 0x001C -#define DSIPHY_CMN_CTRL_1 0x0020 -#define DSIPHY_CMN_CAL_HW_TRIGGER 0x0024 -#define DSIPHY_CMN_CAL_SW_CFG0 0x0028 -#define DSIPHY_CMN_CAL_SW_CFG1 0x002C -#define DSIPHY_CMN_CAL_SW_CFG2 0x0030 -#define DSIPHY_CMN_CAL_HW_CFG0 0x0034 -#define DSIPHY_CMN_CAL_HW_CFG1 0x0038 -#define DSIPHY_CMN_CAL_HW_CFG2 0x003C -#define DSIPHY_CMN_CAL_HW_CFG3 0x0040 -#define DSIPHY_CMN_CAL_HW_CFG4 0x0044 -#define DSIPHY_CMN_PLL_CNTRL 0x0048 -#define DSIPHY_CMN_LDO_CNTRL 0x004C - -#define DSIPHY_CMN_REGULATOR_CAL_STATUS0 0x0064 -#define DSIPHY_CMN_REGULATOR_CAL_STATUS1 0x0068 -#define DSI_MDP_ULPS_CLAMP_ENABLE_OFF 0x0054 - -/* n = 0..3 for data lanes and n = 4 for clock lane - * t for count per lane - */ -#define DSIPHY_DLNX_CFG(n, t) \ - (0x100 + ((t) * 0x04) + ((n) * 0x80)) -#define DSIPHY_DLNX_TIMING_CTRL(n, t) \ - (0x118 + ((t) * 0x04) + ((n) * 0x80)) -#define DSIPHY_DLNX_STRENGTH_CTRL(n, t) \ - (0x138 + ((t) * 0x04) + ((n) * 0x80)) -#define DSIPHY_DLNX_TEST_DATAPATH(n) (0x110 + ((n) * 0x80)) -#define DSIPHY_DLNX_TEST_STR(n) (0x114 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_POLY(n) (0x140 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_SEED0(n) (0x144 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_SEED1(n) (0x148 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_HEAD(n) (0x14C + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_SOT(n) (0x150 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_CTRL0(n) (0x154 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_CTRL1(n) (0x158 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_CTRL2(n) (0x15C + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_CTRL3(n) (0x160 + ((n) * 0x80)) -#define DSIPHY_DLNX_VREG_CNTRL(n) (0x164 + ((n) * 0x80)) -#define DSIPHY_DLNX_HSTX_STR_STATUS(n) (0x168 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_STATUS0(n) (0x16C + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_STATUS1(n) (0x170 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_STATUS2(n) (0x174 + ((n) * 0x80)) -#define DSIPHY_DLNX_BIST_STATUS3(n) (0x178 + ((n) * 0x80)) -#define DSIPHY_DLNX_MISR_STATUS(n) (0x17C + ((n) * 0x80)) - -#define DSIPHY_PLL_CLKBUFLR_EN 0x041C -#define DSIPHY_PLL_PLL_BANDGAP 0x0508 - -/* dynamic refresh control registers */ -#define DSI_DYN_REFRESH_CTRL 0x000 -#define DSI_DYN_REFRESH_PIPE_DELAY 0x004 -#define DSI_DYN_REFRESH_PIPE_DELAY2 0x008 -#define DSI_DYN_REFRESH_PLL_DELAY 0x00C -#define DSI_DYN_REFRESH_STATUS 0x010 -#define DSI_DYN_REFRESH_PLL_CTRL0 0x014 -#define DSI_DYN_REFRESH_PLL_CTRL1 0x018 -#define DSI_DYN_REFRESH_PLL_CTRL2 0x01C -#define DSI_DYN_REFRESH_PLL_CTRL3 0x020 -#define DSI_DYN_REFRESH_PLL_CTRL4 0x024 -#define DSI_DYN_REFRESH_PLL_CTRL5 0x028 -#define DSI_DYN_REFRESH_PLL_CTRL6 0x02C -#define DSI_DYN_REFRESH_PLL_CTRL7 0x030 -#define DSI_DYN_REFRESH_PLL_CTRL8 0x034 -#define DSI_DYN_REFRESH_PLL_CTRL9 0x038 -#define DSI_DYN_REFRESH_PLL_CTRL10 0x03C -#define DSI_DYN_REFRESH_PLL_CTRL11 0x040 -#define DSI_DYN_REFRESH_PLL_CTRL12 0x044 -#define DSI_DYN_REFRESH_PLL_CTRL13 0x048 -#define DSI_DYN_REFRESH_PLL_CTRL14 0x04C -#define DSI_DYN_REFRESH_PLL_CTRL15 0x050 -#define DSI_DYN_REFRESH_PLL_CTRL16 0x054 -#define DSI_DYN_REFRESH_PLL_CTRL17 0x058 -#define DSI_DYN_REFRESH_PLL_CTRL18 0x05C -#define DSI_DYN_REFRESH_PLL_CTRL19 0x060 -#define DSI_DYN_REFRESH_PLL_CTRL20 0x064 -#define DSI_DYN_REFRESH_PLL_CTRL21 0x068 -#define DSI_DYN_REFRESH_PLL_CTRL22 0x06C -#define DSI_DYN_REFRESH_PLL_CTRL23 0x070 -#define DSI_DYN_REFRESH_PLL_CTRL24 0x074 -#define DSI_DYN_REFRESH_PLL_CTRL25 0x078 -#define DSI_DYN_REFRESH_PLL_CTRL26 0x07C -#define DSI_DYN_REFRESH_PLL_CTRL27 0x080 -#define DSI_DYN_REFRESH_PLL_CTRL28 0x084 -#define DSI_DYN_REFRESH_PLL_CTRL29 0x088 -#define DSI_DYN_REFRESH_PLL_CTRL30 0x08C -#define DSI_DYN_REFRESH_PLL_CTRL31 0x090 -#define DSI_DYN_REFRESH_PLL_UPPER_ADDR 0x094 -#define DSI_DYN_REFRESH_PLL_UPPER_ADDR2 0x098 - -#define DSIPHY_DLN0_CFG1 0x0104 -#define DSIPHY_DLN0_TIMING_CTRL_4 0x0118 -#define DSIPHY_DLN0_TIMING_CTRL_5 0x011C -#define DSIPHY_DLN0_TIMING_CTRL_6 0x0120 -#define DSIPHY_DLN0_TIMING_CTRL_7 0x0124 -#define DSIPHY_DLN0_TIMING_CTRL_8 0x0128 - -#define DSIPHY_DLN1_CFG1 0x0184 -#define DSIPHY_DLN1_TIMING_CTRL_4 0x0198 -#define DSIPHY_DLN1_TIMING_CTRL_5 0x019C -#define DSIPHY_DLN1_TIMING_CTRL_6 0x01A0 -#define DSIPHY_DLN1_TIMING_CTRL_7 0x01A4 -#define DSIPHY_DLN1_TIMING_CTRL_8 0x01A8 - -#define DSIPHY_DLN2_CFG1 0x0204 -#define DSIPHY_DLN2_TIMING_CTRL_4 0x0218 -#define DSIPHY_DLN2_TIMING_CTRL_5 0x021C -#define DSIPHY_DLN2_TIMING_CTRL_6 0x0220 -#define DSIPHY_DLN2_TIMING_CTRL_7 0x0224 -#define DSIPHY_DLN2_TIMING_CTRL_8 0x0228 - -#define DSIPHY_DLN3_CFG1 0x0284 -#define DSIPHY_DLN3_TIMING_CTRL_4 0x0298 -#define DSIPHY_DLN3_TIMING_CTRL_5 0x029C -#define DSIPHY_DLN3_TIMING_CTRL_6 0x02A0 -#define DSIPHY_DLN3_TIMING_CTRL_7 0x02A4 -#define DSIPHY_DLN3_TIMING_CTRL_8 0x02A8 - -#define DSIPHY_CKLN_CFG1 0x0304 -#define DSIPHY_CKLN_TIMING_CTRL_4 0x0318 -#define DSIPHY_CKLN_TIMING_CTRL_5 0x031C -#define DSIPHY_CKLN_TIMING_CTRL_6 0x0320 -#define DSIPHY_CKLN_TIMING_CTRL_7 0x0324 -#define DSIPHY_CKLN_TIMING_CTRL_8 0x0328 - -#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c -/** - * regulator_enable() - enable regulators for DSI PHY - * @phy: Pointer to DSI PHY hardware object. - * @reg_cfg: Regulator configuration for all DSI lanes. - */ -void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy, - struct dsi_phy_per_lane_cfgs *reg_cfg) -{ - int i; - bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map); - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) - DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), reg_cfg->lane[i][0]); - - if (is_split_link) - DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1), - reg_cfg->lane[DSI_LOGICAL_CLOCK_LANE][0]); - - /* make sure all values are written to hardware */ - wmb(); - - DSI_PHY_DBG(phy, "Phy regulators enabled\n"); -} - -/** - * regulator_disable() - disable regulators - * @phy: Pointer to DSI PHY hardware object. - */ -void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy) -{ - DSI_PHY_DBG(phy, "Phy regulators disabled\n"); -} - -/** - * enable() - Enable PHY hardware - * @phy: Pointer to DSI PHY hardware object. - * @cfg: Per lane configurations for timing, strength and lane - * configurations. - */ -void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy, - struct dsi_phy_cfg *cfg) -{ - int i, j; - struct dsi_phy_per_lane_cfgs *lanecfg = &cfg->lanecfg; - struct dsi_phy_per_lane_cfgs *timing = &cfg->timing; - struct dsi_phy_per_lane_cfgs *strength = &cfg->strength; - u32 data; - bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map); - - DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C); - - DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0x1); - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { - for (j = 0; j < lanecfg->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_CFG(i, j), - lanecfg->lane[i][j]); - - DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i), 0x88); - - for (j = 0; j < timing->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i, j), - timing->lane[i][j]); - - for (j = 0; j < strength->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j), - strength->lane[i][j]); - } - - if (is_split_link) { - i = DSI_LOGICAL_CLOCK_LANE; - - for (j = 0; j < lanecfg->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_CFG(i+1, j), - lanecfg->lane[i][j]); - - DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i+1), 0x0); - DSI_W32(phy, DSIPHY_DLNX_TEST_DATAPATH(i+1), 0x88); - - for (j = 0; j < timing->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i+1, j), - timing->lane[i][j]); - - for (j = 0; j < strength->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j), - strength->lane[i][j]); - - /* enable split link for cmn clk cfg1 */ - data = DSI_R32(phy, DSIPHY_CMN_CLK_CFG1); - data |= BIT(1); - DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, data); - - } - - /* make sure all values are written to hardware before enabling phy */ - wmb(); - - DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x80); - udelay(100); - DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x00); - - data = DSI_R32(phy, DSIPHY_CMN_GLBL_TEST_CTRL); - - switch (cfg->pll_source) { - case DSI_PLL_SOURCE_STANDALONE: - DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x01); - data &= ~BIT(2); - break; - case DSI_PLL_SOURCE_NATIVE: - DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x03); - data &= ~BIT(2); - break; - case DSI_PLL_SOURCE_NON_NATIVE: - DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x00); - data |= BIT(2); - break; - default: - break; - } - - DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, data); - - /* Enable bias current for pll1 during split display case */ - if (cfg->pll_source == DSI_PLL_SOURCE_NON_NATIVE) - DSI_W32(phy, DSIPHY_PLL_PLL_BANDGAP, 0x3); - - DSI_PHY_DBG(phy, "Phy enabled\n"); -} - -/** - * disable() - Disable PHY hardware - * @phy: Pointer to DSI PHY hardware object. - */ -void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy, - struct dsi_phy_cfg *cfg) -{ - DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0); - DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0); - DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0); - DSI_PHY_DBG(phy, "Phy disabled\n"); -} - -/** - * dsi_phy_hw_v2_0_idle_on() - Enable DSI PHY hardware during idle screen - * @phy: Pointer to DSI PHY hardware object. - */ -void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg) -{ - int i = 0, j; - struct dsi_phy_per_lane_cfgs *strength = &cfg->strength; - bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map); - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { - for (j = 0; j < strength->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j), - strength->lane[i][j]); - } - if (is_split_link) { - i = DSI_LOGICAL_CLOCK_LANE; - for (j = 0; j < strength->count_per_lane; j++) - DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j), - strength->lane[i][j]); - } - wmb(); /* make sure write happens */ - DSI_PHY_DBG(phy, "Phy enabled out of idle screen\n"); -} - - -/** - * dsi_phy_hw_v2_0_idle_off() - Disable DSI PHY hardware during idle screen - * @phy: Pointer to DSI PHY hardware object. - */ -void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy) -{ - int i = 0; - bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map); - - DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f); - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) - DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), 0x1c); - if (is_split_link) - DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1), - 0x1c); - - DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C); - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) - DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, 1), 0x0); - if (is_split_link) - DSI_W32(phy, - DSIPHY_DLNX_STRENGTH_CTRL(DSI_LOGICAL_CLOCK_LANE+1, 1), 0x0); - - wmb(); /* make sure write happens */ - DSI_PHY_DBG(phy, "Phy disabled during idle screen\n"); -} - -int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg, - u32 *timing_val, u32 size) -{ - int i = 0, j = 0; - - if (size != (DSI_LANE_MAX * DSI_MAX_SETTINGS)) { - DSI_ERR("Unexpected timing array size %d\n", size); - return -EINVAL; - } - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { - for (j = 0; j < DSI_MAX_SETTINGS; j++) { - timing_cfg->lane[i][j] = *timing_val; - timing_val++; - } - } - return 0; -} - -void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable) -{ - u32 clamp_reg = 0; - - if (!phy->phy_clamp_base) { - DSI_PHY_DBG(phy, "phy_clamp_base NULL\n"); - return; - } - - if (enable) { - clamp_reg |= BIT(0); - DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF, - clamp_reg); - DSI_PHY_DBG(phy, "clamp enabled\n"); - } else { - clamp_reg &= ~BIT(0); - DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF, - clamp_reg); - DSI_PHY_DBG(phy, "clamp disabled\n"); - } -} - -void dsi_phy_hw_v2_0_dyn_refresh_config(struct dsi_phy_hw *phy, - struct dsi_phy_cfg *cfg, bool is_master) -{ - u32 glbl_tst_cntrl; - - if (is_master) { - glbl_tst_cntrl = DSI_R32(phy, DSIPHY_CMN_GLBL_TEST_CTRL); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL0, - DSIPHY_CMN_GLBL_TEST_CTRL, - DSIPHY_PLL_PLL_BANDGAP, - glbl_tst_cntrl | BIT(1), 0x1); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL1, - DSIPHY_PLL_RESETSM_CNTRL5, - DSIPHY_PLL_PLL_BANDGAP, 0x0D, 0x03); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL2, - DSIPHY_PLL_RESETSM_CNTRL5, - DSIPHY_CMN_PLL_CNTRL, 0x1D, 0x00); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL3, - DSIPHY_CMN_CTRL_1, DSIPHY_DLN0_CFG1, 0x20, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL4, - DSIPHY_DLN1_CFG1, DSIPHY_DLN2_CFG1, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL5, - DSIPHY_DLN3_CFG1, DSIPHY_CKLN_CFG1, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL6, - DSIPHY_DLN0_TIMING_CTRL_4, - DSIPHY_DLN1_TIMING_CTRL_4, - cfg->timing.lane[0][0], cfg->timing.lane[1][0]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL7, - DSIPHY_DLN2_TIMING_CTRL_4, - DSIPHY_DLN3_TIMING_CTRL_4, - cfg->timing.lane[2][0], cfg->timing.lane[3][0]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL8, - DSIPHY_CKLN_TIMING_CTRL_4, - DSIPHY_DLN0_TIMING_CTRL_5, - cfg->timing.lane[4][0], cfg->timing.lane[0][1]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL9, - DSIPHY_DLN1_TIMING_CTRL_5, - DSIPHY_DLN2_TIMING_CTRL_5, - cfg->timing.lane[1][1], cfg->timing.lane[2][1]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL10, - DSIPHY_DLN3_TIMING_CTRL_5, - DSIPHY_CKLN_TIMING_CTRL_5, - cfg->timing.lane[3][1], cfg->timing.lane[4][1]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL11, - DSIPHY_DLN0_TIMING_CTRL_6, - DSIPHY_DLN1_TIMING_CTRL_6, - cfg->timing.lane[0][2], cfg->timing.lane[1][2]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL12, - DSIPHY_DLN2_TIMING_CTRL_6, - DSIPHY_DLN3_TIMING_CTRL_6, - cfg->timing.lane[2][2], cfg->timing.lane[3][2]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL13, - DSIPHY_CKLN_TIMING_CTRL_6, - DSIPHY_DLN0_TIMING_CTRL_7, - cfg->timing.lane[4][2], cfg->timing.lane[0][3]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL14, - DSIPHY_DLN1_TIMING_CTRL_7, - DSIPHY_DLN2_TIMING_CTRL_7, - cfg->timing.lane[1][3], cfg->timing.lane[2][3]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL15, - DSIPHY_DLN3_TIMING_CTRL_7, - DSIPHY_CKLN_TIMING_CTRL_7, - cfg->timing.lane[3][3], cfg->timing.lane[4][3]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, - DSI_DYN_REFRESH_PLL_CTRL16, - DSIPHY_DLN0_TIMING_CTRL_8, - DSIPHY_DLN1_TIMING_CTRL_8, - cfg->timing.lane[0][4], cfg->timing.lane[1][4]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL17, - DSIPHY_DLN2_TIMING_CTRL_8, - DSIPHY_DLN3_TIMING_CTRL_8, - cfg->timing.lane[2][4], cfg->timing.lane[3][4]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL18, - DSIPHY_CKLN_TIMING_CTRL_8, DSIPHY_CMN_CTRL_1, - cfg->timing.lane[4][4], 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL30, - DSIPHY_CMN_GLBL_TEST_CTRL, - DSIPHY_CMN_GLBL_TEST_CTRL, - ((glbl_tst_cntrl) & (~BIT(2))), - ((glbl_tst_cntrl) & (~BIT(2)))); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL31, - DSIPHY_CMN_GLBL_TEST_CTRL, - DSIPHY_CMN_GLBL_TEST_CTRL, - ((glbl_tst_cntrl) & (~BIT(2))), - ((glbl_tst_cntrl) & (~BIT(2)))); - } else { - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL0, - DSIPHY_DLN0_CFG1, DSIPHY_DLN1_CFG1, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL1, - DSIPHY_DLN2_CFG1, DSIPHY_DLN3_CFG1, 0x0, 0x0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL2, - DSIPHY_CKLN_CFG1, DSIPHY_DLN0_TIMING_CTRL_4, - 0x0, cfg->timing.lane[0][0]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL3, - DSIPHY_DLN1_TIMING_CTRL_4, - DSIPHY_DLN2_TIMING_CTRL_4, - cfg->timing.lane[1][0], cfg->timing.lane[2][0]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL4, - DSIPHY_DLN3_TIMING_CTRL_4, - DSIPHY_CKLN_TIMING_CTRL_4, - cfg->timing.lane[3][0], cfg->timing.lane[4][0]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL5, - DSIPHY_DLN0_TIMING_CTRL_5, - DSIPHY_DLN1_TIMING_CTRL_5, - cfg->timing.lane[0][1], cfg->timing.lane[1][1]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL6, - DSIPHY_DLN2_TIMING_CTRL_5, - DSIPHY_DLN3_TIMING_CTRL_5, - cfg->timing.lane[2][1], cfg->timing.lane[3][1]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL7, - DSIPHY_CKLN_TIMING_CTRL_5, - DSIPHY_DLN0_TIMING_CTRL_6, - cfg->timing.lane[4][1], cfg->timing.lane[0][2]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL8, - DSIPHY_DLN1_TIMING_CTRL_6, - DSIPHY_DLN2_TIMING_CTRL_6, - cfg->timing.lane[1][2], cfg->timing.lane[2][2]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL9, - DSIPHY_DLN3_TIMING_CTRL_6, - DSIPHY_CKLN_TIMING_CTRL_6, - cfg->timing.lane[3][2], cfg->timing.lane[4][2]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL10, - DSIPHY_DLN0_TIMING_CTRL_7, - DSIPHY_DLN1_TIMING_CTRL_7, - cfg->timing.lane[0][3], cfg->timing.lane[1][3]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL11, - DSIPHY_DLN2_TIMING_CTRL_7, - DSIPHY_DLN3_TIMING_CTRL_7, - cfg->timing.lane[2][3], cfg->timing.lane[3][3]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL12, - DSIPHY_CKLN_TIMING_CTRL_7, - DSIPHY_DLN0_TIMING_CTRL_8, - cfg->timing.lane[4][3], cfg->timing.lane[0][4]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL13, - DSIPHY_DLN1_TIMING_CTRL_8, - DSIPHY_DLN2_TIMING_CTRL_8, - cfg->timing.lane[1][4], cfg->timing.lane[2][4]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL14, - DSIPHY_DLN3_TIMING_CTRL_8, - DSIPHY_CKLN_TIMING_CTRL_8, - cfg->timing.lane[3][4], cfg->timing.lane[4][4]); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL15, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL16, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL17, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL18, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL19, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL20, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL21, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL22, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL23, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL24, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL25, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL26, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL27, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL28, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL29, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL30, - 0x0110, 0x0110, 0, 0); - DSI_DYN_REF_REG_W(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_CTRL31, - 0x0110, 0x0110, 0, 0); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_UPPER_ADDR, - 0x0); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_UPPER_ADDR2, - 0x0); - } - - wmb(); /* make sure phy timings are updated*/ -} - -void dsi_phy_hw_v2_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy, - struct dsi_dyn_clk_delay *delay) -{ - if (!delay) - return; - - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PIPE_DELAY, - delay->pipe_delay); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PIPE_DELAY2, - delay->pipe_delay2); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_PLL_DELAY, - delay->pll_delay); -} - -void dsi_phy_hw_v2_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset) -{ - u32 reg; - - /* - * if no offset is mentioned then this means we want to clear - * the dynamic refresh ctrl register which is the last step - * of dynamic refresh sequence. - */ - if (!offset) { - reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL); - reg &= ~(BIT(0) | BIT(8)); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg); - wmb(); /* ensure dynamic fps is cleared */ - return; - } - - if (offset & BIT(DYN_REFRESH_INTF_SEL)) { - reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL); - reg |= BIT(13); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg); - } - - if (offset & BIT(DYN_REFRESH_SWI_CTRL)) { - reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL); - reg |= BIT(0); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg); - } - - if (offset & BIT(DYN_REFRESH_SW_TRIGGER)) { - reg = DSI_GEN_R32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL); - reg |= BIT(8); - DSI_GEN_W32(phy->dyn_pll_base, DSI_DYN_REFRESH_CTRL, reg); - wmb(); /* ensure dynamic fps is triggered */ - } -} - -int dsi_phy_hw_v2_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings, - u32 *dst, u32 size) -{ - int i, j, count = 0; - - if (!timings || !dst || !size) - return -EINVAL; - - if (size != (DSI_LANE_MAX * DSI_MAX_SETTINGS)) { - pr_err("size mis-match\n"); - return -EINVAL; - } - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { - for (j = 0; j < DSI_MAX_SETTINGS; j++) { - dst[count] = timings->lane[i][j]; - count++; - } - } - - return 0; -} diff --git a/msm/dsi/dsi_phy_timing_calc.c b/msm/dsi/dsi_phy_timing_calc.c index be1d8b7899..2d407930d6 100644 --- a/msm/dsi/dsi_phy_timing_calc.c +++ b/msm/dsi/dsi_phy_timing_calc.c @@ -974,22 +974,6 @@ int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy, phy->ops.timing_ops = ops; switch (version) { - case DSI_PHY_VERSION_2_0: - ops->get_default_phy_params = - dsi_phy_hw_v2_0_get_default_phy_params; - ops->calc_clk_zero = - dsi_phy_hw_v2_0_calc_clk_zero; - ops->calc_clk_trail_rec_min = - dsi_phy_hw_v2_0_calc_clk_trail_rec_min; - ops->calc_clk_trail_rec_max = - dsi_phy_hw_v2_0_calc_clk_trail_rec_max; - ops->calc_hs_zero = - dsi_phy_hw_v2_0_calc_hs_zero; - ops->calc_hs_trail = - dsi_phy_hw_v2_0_calc_hs_trail; - ops->update_timing_params = - dsi_phy_hw_v2_0_update_timing_params; - break; case DSI_PHY_VERSION_3_0: ops->get_default_phy_params = dsi_phy_hw_v3_0_get_default_phy_params; @@ -1025,9 +1009,6 @@ int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy, ops->update_timing_params = dsi_phy_hw_v4_0_update_timing_params; break; - case DSI_PHY_VERSION_0_0_HPM: - case DSI_PHY_VERSION_0_0_LPM: - case DSI_PHY_VERSION_1_0: default: kfree(ops); return -ENOTSUPP; diff --git a/msm/dsi/dsi_phy_timing_v2_0.c b/msm/dsi/dsi_phy_timing_v2_0.c deleted file mode 100644 index 383999395b..0000000000 --- a/msm/dsi/dsi_phy_timing_v2_0.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - */ - -#include "dsi_phy_timing_calc.h" - -void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params, - u32 phy_type) -{ - params->clk_prep_buf = 50; - params->clk_zero_buf = 2; - params->clk_trail_buf = 30; - params->hs_prep_buf = 50; - params->hs_zero_buf = 10; - params->hs_trail_buf = 30; - params->hs_rqst_buf = 0; - params->hs_exit_buf = 10; -} - -int32_t dsi_phy_hw_v2_0_calc_clk_zero(s64 rec_temp1, s64 mult) -{ - s64 rec_temp2, rec_temp3; - - rec_temp2 = (rec_temp1 - (11 * mult)); - rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult); - return (div_s64(rec_temp3, mult) - 3); -} - -int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_min(s64 temp_mul, - s64 frac, s64 mult) -{ - s64 rec_temp1, rec_temp2, rec_temp3; - - rec_temp1 = temp_mul + frac + (3 * mult); - rec_temp2 = div_s64(rec_temp1, 8); - rec_temp3 = roundup64(rec_temp2, mult); - - return div_s64(rec_temp3, mult); -} - -int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_max(s64 temp1, s64 mult) -{ - s64 rec_temp2, rec_temp3; - - rec_temp2 = temp1 + (3 * mult); - rec_temp3 = rec_temp2 / 8; - return div_s64(rec_temp3, mult); - -} - -int32_t dsi_phy_hw_v2_0_calc_hs_zero(s64 temp1, s64 mult) -{ - s64 rec_temp2, rec_temp3, rec_min; - - rec_temp2 = temp1 - (11 * mult); - rec_temp3 = roundup64((rec_temp2 / 8), mult); - rec_min = rec_temp3 - (3 * mult); - return div_s64(rec_min, mult); -} - -void dsi_phy_hw_v2_0_calc_hs_trail(struct phy_clk_params *clk_params, - struct phy_timing_desc *desc) -{ - s64 rec_temp1; - struct timing_entry *t = &desc->hs_trail; - - t->rec_min = DIV_ROUND_UP( - ((t->mipi_min * clk_params->bitclk_mbps) + - (3 * clk_params->tlpx_numer_ns)), - (8 * clk_params->tlpx_numer_ns)); - - rec_temp1 = ((t->mipi_max * clk_params->bitclk_mbps) + - (3 * clk_params->tlpx_numer_ns)); - t->rec_max = DIV_ROUND_UP_ULL(rec_temp1, - (8 * clk_params->tlpx_numer_ns)); -} - -void dsi_phy_hw_v2_0_update_timing_params( - struct dsi_phy_per_lane_cfgs *timing, - struct phy_timing_desc *desc, u32 phy_type) -{ - int i = 0; - - for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) { - timing->lane[i][0] = desc->hs_exit.reg_value; - - if (i == DSI_LOGICAL_CLOCK_LANE) - timing->lane[i][1] = desc->clk_zero.reg_value; - else - timing->lane[i][1] = desc->hs_zero.reg_value; - - if (i == DSI_LOGICAL_CLOCK_LANE) - timing->lane[i][2] = desc->clk_prepare.reg_value; - else - timing->lane[i][2] = desc->hs_prepare.reg_value; - - if (i == DSI_LOGICAL_CLOCK_LANE) - timing->lane[i][3] = desc->clk_trail.reg_value; - else - timing->lane[i][3] = desc->hs_trail.reg_value; - - if (i == DSI_LOGICAL_CLOCK_LANE) - timing->lane[i][4] = desc->hs_rqst_clk.reg_value; - else - timing->lane[i][4] = desc->hs_rqst.reg_value; - - timing->lane[i][5] = 0x2; - timing->lane[i][6] = 0x4; - timing->lane[i][7] = 0xA0; - DSI_DEBUG("[%d][%d %d %d %d %d]\n", i, timing->lane[i][0], - timing->lane[i][1], - timing->lane[i][2], - timing->lane[i][3], - timing->lane[i][4]); - } - timing->count_per_lane = 8; -}