qcacmn: Add Waikiki monitor HAL processing
Add Waikiki monitor HAL processing CRs-Fixed: 3073467 Change-Id: I2b1768b827f34785effed6c076a099628870e2a5
This commit is contained in:

committed by
Madan Koyyalamudi

parent
482fba652b
commit
f17d789fa6
@@ -43,7 +43,7 @@ dp_rx_process_pktlog_be(struct dp_soc *soc, struct dp_pdev *pdev,
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qdf_nbuf_t nbuf = NULL;
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enum WDI_EVENT pktlog_mode = WDI_NO_VAL;
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if (mon_pdev->dp_peer_based_pktlog &&
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if (!mon_pdev->dp_peer_based_pktlog &&
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(mon_pdev->rx_pktlog_mode == DP_RX_PKTLOG_DISABLED)) {
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return QDF_STATUS_E_INVAL;
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}
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -20,7 +20,6 @@
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#ifndef _HAL_BE_HW_INTERNAL_H_
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#define _HAL_BE_HW_INTERNAL_H_
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#include "hal_hw_headers.h"
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#include "wcss_seq_hwioreg_umac.h"
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#include "phyrx_location.h"
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#include "receive_rssi_info.h"
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@@ -22,6 +22,7 @@
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#include "qdf_types.h"
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#include "hal_internal.h"
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#include "hal_rx.h"
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#include "hal_hw_headers.h"
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#include <target_type.h>
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@@ -77,6 +78,8 @@
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#define HAL_TLV_STATUS_MPDU_END 6
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#define HAL_TLV_STATUS_MSDU_START 7
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#define HAL_TLV_STATUS_MSDU_END 8
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#define HAL_TLV_STATUS_MON_BUF_ADDR 9
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#define HAL_TLV_STATUS_MPDU_START 10
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#define HAL_MAX_UL_MU_USERS 37
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@@ -190,6 +193,100 @@
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#define HAL_RX_FRAME_CTRL_TYPE_CTRL 0x1
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#define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2
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/**
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* hal_dl_ul_flag - flag to indicate UL/DL
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* @dl_ul_flag_is_dl_or_tdls: DL
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* @dl_ul_flag_is_ul: UL
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*/
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enum hal_dl_ul_flag {
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dl_ul_flag_is_dl_or_tdls,
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dl_ul_flag_is_ul,
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};
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/*
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* hal_eht_ppdu_sig_cmn_type - PPDU type
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* @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU
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* @eht_ppdu_sig_su: SU PPDU
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* @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU
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*/
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enum hal_eht_ppdu_sig_cmn_type {
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eht_ppdu_sig_tb_or_dl_ofdma,
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eht_ppdu_sig_su,
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eht_ppdu_sig_dl_mu_mimo,
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};
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/*
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* hal_mon_packet_info - packet info
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* @sw_cookie: 64-bit SW desc virtual address
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* @dma_length: packet DMA length
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* @msdu_continuation: msdu continulation in next buffer
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* @truncated: packet is truncated
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*/
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struct hal_mon_packet_info {
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uint64_t sw_cookie;
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uint16_t dma_length;
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bool msdu_continuation;
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bool truncated;
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};
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/*
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* hal_rx_mon_msdu_info - msdu info
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* @first_buffer: first buffer of msdu
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* @last_buffer: last buffer of msdu
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* @first_mpdu: first MPDU
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* @mpdu_length_err: MPDU length error
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* @fcs_err: FCS error
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* @first_msdu: first msdu
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* @decap_type: decap type
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* @last_msdu: last msdu
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* @buffer_len: buffer len
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* @frag_len: frag len
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* @msdu_len: msdu len
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* @msdu_index: msdu index
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* @user_rssi: user rssi
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* @l3_header_padding: L3 padding header
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* @stbc: stbc enabled
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* @sgi: SGI value
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* @reception_type: reception type
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*/
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struct hal_rx_mon_msdu_info {
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uint8_t first_buffer;
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uint8_t last_buffer;
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uint8_t first_mpdu;
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uint8_t mpdu_length_err;
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uint8_t fcs_err;
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uint8_t first_msdu;
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uint8_t decap_type;
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uint8_t last_msdu;
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uint16_t buffer_len;
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uint16_t frag_len;
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uint16_t msdu_len;
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uint8_t msdu_index;
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int8_t user_rssi;
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uint8_t l3_header_padding;
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uint8_t stbc;
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uint8_t sgi;
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uint8_t reception_type;
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};
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/*
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* hal_rx_mon_mpdu_info - MPDU info
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* @decap_type: decap_type
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* @mpdu_length_err: MPDU length error
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* @fcs_err: FCS error
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* @overflow_err: overflow error
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* @decrypt_err: decrypt error
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* @mpdu_start_received: MPDU start received
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*/
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struct hal_rx_mon_mpdu_info {
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uint8_t decap_type;
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bool mpdu_length_err;
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bool fcs_err;
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bool overflow_err;
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bool decrypt_err;
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bool mpdu_start_received;
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};
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/**
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* struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info
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*
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@@ -504,7 +601,7 @@ enum {
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*/
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struct hal_rx_ppdu_common_info {
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uint32_t ppdu_id;
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uint32_t ppdu_timestamp;
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uint64_t ppdu_timestamp;
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uint32_t mpdu_cnt_fcs_ok;
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uint32_t mpdu_cnt_fcs_err;
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uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
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@@ -1126,6 +1223,20 @@ struct hal_rx_ppdu_info {
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struct hal_rx_tlv_aggr_info tlv_aggr;
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/* EHT SIG user info */
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uint32_t eht_sig_user_info;
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/*per user mpdu count */
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uint16_t mpdu_count[HAL_MAX_UL_MU_USERS];
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/*per user msdu count */
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uint16_t msdu_count[HAL_MAX_UL_MU_USERS];
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/* Placeholder to update per user last processed msdu’s info */
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struct hal_rx_mon_msdu_info msdu[HAL_MAX_UL_MU_USERS];
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/* Placeholder to update per user last processed mpdu’s info */
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struct hal_rx_mon_mpdu_info mpdu_info[HAL_MAX_UL_MU_USERS];
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/* placeholder to hold packet buffer info */
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struct hal_mon_packet_info packet_info;
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/* per user per MPDU queue */
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qdf_nbuf_t mpdu_q[HAL_MAX_UL_MU_USERS][HAL_RX_MAX_MPDU];
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/* ppdu info list element */
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TAILQ_ENTRY(hal_rx_ppdu_info) ppdu_list_elem;
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};
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static inline uint32_t
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@@ -20,7 +20,6 @@
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#define _HAL_GENERIC_API_H_
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#include <hal_rx.h>
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#include "hal_api_mon.h"
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/**
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* hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value
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@@ -33,7 +33,6 @@
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#include "rx_flow_search_entry.h"
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#include "hal_rx_flow_info.h"
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#include "hal_be_api.h"
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#include "hal_be_api_mon.h"
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#include "reo_destination_ring_with_pn.h"
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#include <hal_be_rx.h>
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@@ -124,6 +123,7 @@ struct tcl_data_cmd gtcl_data_symbol __attribute__((used));
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#include <hal_generic_api.h>
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#include <hal_be_generic_api.h>
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#include "hal_be_api_mon.h"
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#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
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@@ -48,34 +48,6 @@
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#include <hal_be_rx.h>
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
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RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
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RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK
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#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
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RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB
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#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
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PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
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#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
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PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
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#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
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PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
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#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
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PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
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#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
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PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
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#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
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PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
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#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
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PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
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#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
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PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
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#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
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PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
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#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
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PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
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#define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
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PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
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#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
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RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
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#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
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@@ -127,6 +99,8 @@
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#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
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WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
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#include "hal_be_api_mon.h"
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#ifdef CONFIG_WIFI_EMULATION_WIFI_3_0
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#define CMEM_REG_BASE 0x0010e000
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