qcacmn: Add hal_rx_msdu_end_l3_hdr_padding_get API

Implement hal_rx_msdu_end_l3_hdr_padding_get API
based on the chipset as the macro to retrieve
sa_idx value is chipset dependent.

Change-Id: Ice1fc2d70e339dc1d80fa6f34f37c5a7aa074be5
CRs-Fixed: 2522133
This commit is contained in:
Venkata Sharath Chandra Manchala
2019-09-20 17:25:21 -07:00
committed by nshrivas
parent 43d563277d
commit f05b2ae5c2
16 changed files with 164 additions and 19 deletions

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@@ -1601,7 +1601,7 @@ void dp_rx_deliver_to_stack_no_peer(struct dp_soc *soc, qdf_nbuf_t nbuf)
rx_tlv_hdr = qdf_nbuf_data(nbuf);
l2_hdr_offset =
hal_rx_msdu_end_l3_hdr_padding_get(rx_tlv_hdr);
hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc, rx_tlv_hdr);
msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;
@@ -2045,7 +2045,8 @@ done:
next = nbuf->next;
} else {
l2_hdr_offset =
hal_rx_msdu_end_l3_hdr_padding_get(rx_tlv_hdr);
hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc,
rx_tlv_hdr);
msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;

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@@ -708,7 +708,8 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
rx_tlv_hdr));
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(rx_tlv_hdr);
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc,
rx_tlv_hdr);
msdu_len = hal_rx_msdu_start_msdu_len_get(rx_tlv_hdr);
pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;
@@ -905,7 +906,8 @@ dp_rx_process_rxdma_err(struct dp_soc *soc, qdf_nbuf_t nbuf,
qdf_assert(0);
}
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(rx_tlv_hdr);
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc,
rx_tlv_hdr);
msdu_len = hal_rx_msdu_start_msdu_len_get(rx_tlv_hdr);
pkt_len = msdu_len + l2_hdr_offset + RX_PKT_TLVS_LEN;

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@@ -455,7 +455,7 @@ dp_rx_mon_mpdu_pop(struct dp_soc *soc, uint32_t mac_id,
* header begins.
*/
l2_hdr_offset =
hal_rx_msdu_end_l3_hdr_padding_get(data);
hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc, data);
rx_buf_size = rx_pkt_offset + l2_hdr_offset
+ frag_len;
@@ -529,14 +529,14 @@ next_msdu:
}
static inline
void dp_rx_msdus_set_payload(qdf_nbuf_t msdu)
void dp_rx_msdus_set_payload(struct dp_soc *soc, qdf_nbuf_t msdu)
{
uint8_t *data;
uint32_t rx_pkt_offset, l2_hdr_offset;
data = qdf_nbuf_data(msdu);
rx_pkt_offset = HAL_RX_MON_HW_RX_DESC_SIZE();
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(data);
l2_hdr_offset = hal_rx_msdu_end_l3_hdr_padding_get(soc->hal_soc, data);
qdf_nbuf_pull_head(msdu, rx_pkt_offset + l2_hdr_offset);
}
@@ -596,7 +596,7 @@ qdf_nbuf_t dp_rx_mon_restitch_mpdu_from_msdus(struct dp_soc *soc,
* - but the RX status is usually enough
*/
dp_rx_msdus_set_payload(head_msdu);
dp_rx_msdus_set_payload(soc, head_msdu);
QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
"[%s][%d] decap format raw head %pK head->next %pK last_msdu %pK last_msdu->next %pK",
@@ -613,7 +613,7 @@ qdf_nbuf_t dp_rx_mon_restitch_mpdu_from_msdus(struct dp_soc *soc,
while (msdu) {
dp_rx_msdus_set_payload(msdu);
dp_rx_msdus_set_payload(soc, msdu);
if (is_first_frag) {
is_first_frag = 0;
@@ -772,7 +772,7 @@ qdf_nbuf_t dp_rx_mon_restitch_mpdu_from_msdus(struct dp_soc *soc,
dest += amsdu_pad;
qdf_mem_copy(dest, hdr_desc, msdu_llc_len);
dp_rx_msdus_set_payload(msdu);
dp_rx_msdus_set_payload(soc, msdu);
/* Push the MSDU buffer beyond the decap header */
qdf_nbuf_pull_head(msdu, decap_hdr_pull_bytes);

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@@ -385,6 +385,7 @@ struct hal_hw_txrx_ops {
uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
};
/**

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@@ -1046,15 +1046,12 @@ hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata)
* Return: number of l3 header padding bytes
*/
static inline uint32_t
hal_rx_msdu_end_l3_hdr_padding_get(uint8_t *buf)
hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
}
/**

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@@ -197,6 +197,24 @@ static uint32_t hal_rx_desc_is_first_msdu_6290(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_6290(): API to get_6290 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6290(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
/* init and setup */
hal_srng_dst_hw_init_generic,
@@ -243,6 +261,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
hal_rx_msdu_end_sa_is_valid_get_6290,
hal_rx_msdu_end_sa_idx_get_6290,
hal_rx_desc_is_first_msdu_6290,
hal_rx_msdu_end_l3_hdr_padding_get_6290,
};
struct hal_hw_srng_config hw_srng_table_6290[] = {

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@@ -59,6 +59,12 @@
RX_MSDU_END_13_SA_IDX_MASK, \
RX_MSDU_END_13_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
#if defined(QCA_WIFI_QCA6290_11AX)
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\

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@@ -197,6 +197,24 @@ static uint32_t hal_rx_desc_is_first_msdu_6390(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_6390(): API to get_6390 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6390(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
/* init and setup */
hal_srng_dst_hw_init_generic,
@@ -243,6 +261,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
hal_rx_msdu_end_sa_is_valid_get_6390,
hal_rx_msdu_end_sa_idx_get_6390,
hal_rx_desc_is_first_msdu_6390,
hal_rx_msdu_end_l3_hdr_padding_get_6390,
};
struct hal_hw_srng_config hw_srng_table_6390[] = {

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@@ -59,6 +59,12 @@
RX_MSDU_END_13_SA_IDX_MASK, \
RX_MSDU_END_13_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \

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@@ -103,10 +103,29 @@ static uint32_t hal_rx_desc_is_first_msdu_6490(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_6490(): API to get_6490 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6490(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
/* rx */
hal_rx_get_rx_fragment_number_6490,
hal_rx_msdu_end_da_is_mcbc_get_6490,
hal_rx_msdu_end_sa_is_valid_get_6490,
hal_rx_desc_is_first_msdu_6490,
hal_rx_msdu_end_l3_hdr_padding_get_6490,
};

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@@ -39,3 +39,9 @@
RX_MSDU_END_11_SA_IDX_OFFSET)), \
RX_MSDU_END_11_SA_IDX_MASK, \
RX_MSDU_END_11_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_10_L3_HEADER_PADDING_LSB))

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@@ -191,6 +191,25 @@ static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_8074v1(): API to get_8074v1 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
/* init and setup */
@@ -238,6 +257,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
hal_rx_msdu_end_sa_is_valid_get_8074v1,
hal_rx_msdu_end_sa_idx_get_8074v1,
hal_rx_desc_is_first_msdu_8074v1,
hal_rx_msdu_end_l3_hdr_padding_get_8074v1,
};
struct hal_hw_srng_config hw_srng_table_8074[] = {

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@@ -48,6 +48,11 @@
RX_MSDU_END_13_SA_IDX_MASK, \
RX_MSDU_END_13_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
/*
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS
* Interval from rx_msdu_start

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@@ -192,6 +192,24 @@ static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_8074v2(): API to get_8074v2 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
/* init and setup */
@@ -239,6 +257,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
hal_rx_msdu_end_sa_is_valid_get_8074v2,
hal_rx_msdu_end_sa_idx_get_8074v2,
hal_rx_desc_is_first_msdu_8074v2,
hal_rx_msdu_end_l3_hdr_padding_get_8074v2,
};
struct hal_hw_srng_config hw_srng_table_8074v2[] = {

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@@ -51,6 +51,12 @@
RX_MSDU_END_13_SA_IDX_MASK, \
RX_MSDU_END_13_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \

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@@ -201,6 +201,24 @@ static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr)
return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
}
/**
* hal_rx_msdu_end_l3_hdr_padding_get_9000(): API to get_9000 the
* l3_header padding from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: number of l3 header padding bytes
*/
static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t l3_header_padding;
l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
return l3_header_padding;
}
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
/* init and setup */
@@ -248,6 +266,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
hal_rx_msdu_end_sa_is_valid_get_9000,
hal_rx_msdu_end_sa_idx_get_9000,
hal_rx_desc_is_first_msdu_9000,
hal_rx_msdu_end_l3_hdr_padding_get_9000,
};
struct hal_hw_srng_config hw_srng_table_9000[] = {