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fw-api: Update HW header files to E7 (WCSS_P3R8) for QCA6290

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Update HW include header files to emulation release version E7
from E6. This specifically refers to WCSS_P3R8 folder in P4 in
FW code base. This update is just to keep the host & fw in sync.
There is almost no change to the UMAC header files that host is
concerned about in this update.

Change-Id: I2016a4d8af530971e8afce6526f960dc429ecdfa
CRs-Fixed: 2083827
This commit is contained in:
Debashis Dutt
2017-07-27 16:14:20 -07:00
committed by snandini
parent 51bacbd8b2
commit f0375dd077
16 changed files with 149 additions and 230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
hw/qca6290/v2/HALcomdef.h
View File

@@ -29,7 +29,7 @@ DESCRIPTION:
Edit History
$Header: //depot/prj/qca/lithium/wcss/verif/native/register/include/HALcomdef.h#6 $
$Header: //depot/bringup/ar6k/test_tufello/1.0/Tufello_WIFI_Emu/napier/sandbox/to_randy/wcss/include/HALcomdef.h#1 $
when who what, where, why
-------- --- -----------------------------------------------------------

2
hw/qca6290/v2/com_dtypes.h
View File

@@ -61,7 +61,7 @@ DESCRIPTION
This section contains comments describing changes made to this file.
Notice that changes are listed in reverse chronological order.
$Header: //depot/prj/qca/lithium/wcss/verif/native/register/include/com_dtypes.h#5 $
$Header: //depot/sw/branches/rome_emulation_dev/wlan/mac_e7_r8_0509/lithium-napier-swi/include/com_dtypes.h#1 $
when who what, where, why
-------- --- ----------------------------------------------------------

4
hw/qca6290/v2/he_sig_a_su_info.h
View File

@@ -205,7 +205,7 @@ cp_ltf_size
NOTE:
For QCA proprietary mode
For QC proprietary mode
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
@@ -587,7 +587,7 @@ rx_ndp
NOTE:
For QCA proprietary mode
For QC proprietary mode
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)

5
hw/qca6290/v2/mac_tcl_reg_seq_hwiobase.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

5
hw/qca6290/v2/mac_tcl_reg_seq_hwioreg.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

5
hw/qca6290/v2/reo_reg_seq_hwiobase.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

4
hw/qca6290/v2/reo_reg_seq_hwioreg.h
View File

@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

2
hw/qca6290/v2/rx_timing_offset_info.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the

2
hw/qca6290/v2/rxpcu_ppdu_end_info.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the

5
hw/qca6290/v2/wbm_reg_seq_hwiobase.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

5
hw/qca6290/v2/wbm_reg_seq_hwioreg.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

197
hw/qca6290/v2/wcss_seq_hwiobase.h
View File

@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
@@ -29,7 +29,7 @@
#define __WCSS_SEQ_BASE_H__
#ifdef SCALE_INCLUDES
#include "../../../include/HALhwio.h"
#include "../../../include/HALhwio.h"
#else
#include "msmhwio.h"
#endif
@@ -68,14 +68,8 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x005d5000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x005d5040
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x005d5080
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x005d50c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6080
@@ -90,7 +84,6 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6900
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6940
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x005d7c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400
@@ -99,38 +92,30 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x005dc400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x005dc600
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dc800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dc840
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dc880
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dc8c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x005e0400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x005e0800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x005e8400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x005e8800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9480
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x005f0400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x005f0800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9480
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000
#define SEQ_WCSS_PHYB_OFFSET 0x00600000
#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000
@@ -152,14 +137,8 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x007d4c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x007d5000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x007d5040
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x007d5080
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x007d50c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x007d5400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d6080
@@ -174,7 +153,6 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6900
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6940
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x007d6a00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x007d7c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET 0x007d8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET 0x007d8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET 0x007d8400
@@ -183,38 +161,30 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x007d88c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x007d8940
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x007d8980
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x007dc000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x007dc000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x007dc400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x007dc600
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x007dc800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x007dc840
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x007dc880
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x007dc8c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x007e0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x007e0400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x007e0800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x007e1000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x007e8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x007e8400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x007e8800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x007e9000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x007f0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x007f0400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x007f0800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x007f1000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x007f9000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000
#define SEQ_WCSS_UMAC_OFFSET 0x00a00000
#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000
@@ -379,14 +349,8 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x001d5000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x001d5040
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x001d5080
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x001d50c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080
@@ -401,7 +365,6 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x001d8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x001d8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x001d8400
@@ -410,38 +373,30 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x001d8940
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x001d8980
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x001dc400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x001dc600
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dc800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dc880
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dc8c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000
@@ -451,14 +406,8 @@
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BS_OFFSET 0x00015000
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_BIST_OFFSET 0x00015040
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_PC_OFFSET 0x00015080
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_AC_OFFSET 0x000150c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014400
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080
@@ -473,7 +422,6 @@
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00
#define SEQ_RFA_FROM_WSI_RFA_CMN_DRM_REG_OFFSET 0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400
@@ -482,38 +430,30 @@
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940
#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH1_OFFSET 0x0001c400
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH0_OFFSET 0x0001c600
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0
#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00020400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00020800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00028400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00028800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029480
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00030400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00030800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00038400
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00038800
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039480
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039180
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000
@@ -522,14 +462,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00
#define SEQ_RFA_CMN_BBPLL_BS_OFFSET 0x00001000
#define SEQ_RFA_CMN_BBPLL_BIST_OFFSET 0x00001040
#define SEQ_RFA_CMN_BBPLL_PC_OFFSET 0x00001080
#define SEQ_RFA_CMN_BBPLL_AC_OFFSET 0x000010c0
#define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400
#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000400
#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000800
#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000
#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040
#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080
@@ -544,7 +478,6 @@
#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900
#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940
#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00
#define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00
///////////////////////////////////////////////////////////////////////////////////////////////
@@ -560,19 +493,6 @@
#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_bt
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000
#define SEQ_RFA_BT_BT_CH1_OFFSET 0x00000400
#define SEQ_RFA_BT_BT_CH0_OFFSET 0x00000600
#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800
#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840
#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880
#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block rfa_wl
///////////////////////////////////////////////////////////////////////////////////////////////
@@ -581,25 +501,25 @@
#define SEQ_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x00000400
#define SEQ_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x00000800
#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000
#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300
#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001180
#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000
#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000
#define SEQ_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x00008400
#define SEQ_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x00008800
#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009180
#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009480
#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000
#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009180
#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000
#define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000
#define SEQ_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x00010400
#define SEQ_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x00010800
#define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000
#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300
#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011180
#define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000
#define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000
#define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00018400
#define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x00018800
#define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019180
#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019480
#define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019000
#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019180
#define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000
@@ -626,14 +546,8 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BS_OFFSET 0x001d5000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_BIST_OFFSET 0x001d5040
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_PC_OFFSET 0x001d5080
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_AC_OFFSET 0x001d50c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x001d5400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080
@@ -648,7 +562,6 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_OFFSET 0x001d8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_MC_OFFSET 0x001d8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_RX_OFFSET 0x001d8400
@@ -657,38 +570,30 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x001d88c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x001d8940
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x001d8980
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH1_OFFSET 0x001dc400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_CH0_OFFSET 0x001dc600
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x001dc800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x001dc840
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x001dc880
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x001dc8c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x001e0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH0_OFFSET 0x001e0400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH0_OFFSET 0x001e0800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x001e1000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x001e8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH0_OFFSET 0x001e8400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH0_OFFSET 0x001e8800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x001e9000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x001f0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_2G_CH1_OFFSET 0x001f0400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_2G_CH1_OFFSET 0x001f0800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x001f1000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x001f9000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000

2
hw/qca6290/v2/wcss_version.h
View File

@@ -16,4 +16,4 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
#define WCSS_VERSION 2001
#define WCSS_VERSION 2004

8
hw/qca6290/v2/wfss_ce_reg_seq_hwiobase.h
View File

@@ -16,6 +16,14 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////
#ifndef __WFSS_CE_REG_SEQ_BASE_H__
#define __WFSS_CE_REG_SEQ_BASE_H__

5
hw/qca6290/v2/wfss_ce_reg_seq_hwioreg.h
View File

@@ -16,9 +16,10 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 3/3/2017
// User Name:c_palad
// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/8/2017
// User Name:gunjans
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//