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disp: msm: sde: update vsync soure as part of post modeset

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This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.

Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This commit is contained in:
Narendra Muppalla
2022-04-26 15:16:34 -07:00
parent be3eb851cf
commit f014267f93
1 changed files with 8 additions and 0 deletions
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8
msm/sde/sde_encoder.c
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@@ -2164,6 +2164,14 @@ static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
goto end;
}
/* toggle te bit to update vsync source for sim cmd mode panels */
if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)
&& sde_enc->disp_info.is_te_using_watchdog_timer) {
sde_encoder_control_te(drm_enc, false);
_sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info);
sde_encoder_control_te(drm_enc, true);
}
_sde_encoder_update_rsc_client(drm_enc, true);
SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,