msm: camera: isp: Get default sys cache config from header

Update sys cache config from header for all SFE versions.

CRs-Fixed: 3305569
Change-Id: Iba4470c93e541fb1d969b82eb0c1199b3b7eb7e1
Signed-off-by: Karthik Anantha Ram <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -579,6 +579,7 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
 	 * the minimum
 	 */
 	.latency_buf_allocation = 2048,
+	.sys_cache_default_val  = 0x20,
 	.irq_err_mask           = 0x1,
 	.fs_sync_shift          = 0x5,
 	.constraint_error_info  = &sfe680_bus_rd_constraint_error_info,
@@ -1294,13 +1295,14 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 	.comp_done_shift = {
 		17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 	},
-	.num_comp_grp         = 10,
-	.line_done_cfg        = 0x11,
-	.top_irq_shift        = 0x0,
-	.max_out_res          = CAM_ISP_SFE_OUT_RES_BASE + 13,
-	.pack_align_shift     = 0x5,
-	.max_bw_counter_limit = 0xFF,
-	.irq_err_mask         = 0xD0000000,
+	.num_comp_grp          = 10,
+	.line_done_cfg         = 0x11,
+	.top_irq_shift         = 0x0,
+	.max_out_res           = CAM_ISP_SFE_OUT_RES_BASE + 13,
+	.pack_align_shift      = 0x5,
+	.max_bw_counter_limit  = 0xFF,
+	.sys_cache_default_val = 0x20,
+	.irq_err_mask          = 0xD0000000,
 };
 
 static struct cam_irq_register_set sfe680_top_irq_reg_set[1] = {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h

@@ -821,6 +821,7 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
 	},
 	.top_irq_shift          = 0x1,
 	.latency_buf_allocation = 2048,
+	.sys_cache_default_val  = 0x20,
 	.irq_err_mask           = 0x1,
 	.fs_sync_shift          = 0x5,
 	.constraint_error_info  = &sfe780_bus_rd_constraint_error_info,
@@ -1680,6 +1681,7 @@ static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
 	.max_out_res               = CAM_ISP_SFE_OUT_RES_BASE + 17,
 	.pack_align_shift          = 5,
 	.max_bw_counter_limit      = 0xFF,
+	.sys_cache_default_val     = 0x20,
 	.irq_err_mask              = 0xD0000000,
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe880.h

@@ -860,6 +860,7 @@ static struct cam_sfe_bus_rd_hw_info sfe880_bus_rd_hw_info = {
 	},
 	.top_irq_shift          = 0x1,
 	.latency_buf_allocation = 2048,
+	.sys_cache_default_val  = 0x20,
 	.irq_err_mask           = 0x80000001,
 	.fs_sync_shift          = 0x14,
 	.constraint_error_info  = &sfe880_bus_rd_constraint_error_info,
@@ -1773,6 +1774,7 @@ static struct cam_sfe_bus_wr_hw_info sfe880_bus_wr_hw_info = {
 	.max_out_res            = CAM_ISP_SFE_OUT_RES_BASE + 18,
 	.pack_align_shift       = 5,
 	.max_bw_counter_limit   = 0xFF,
+	.sys_cache_default_val  = 0x20,
 	.irq_err_mask           = 0xD0000000,
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c

@@ -133,6 +133,7 @@ struct cam_sfe_bus_rd_priv {
 	void                               *tasklet_info;
 	uint32_t                            top_irq_shift;
 	uint32_t                            latency_buf_allocation;
+	uint32_t                            sys_cache_default_cfg;
 };
 
 static void cam_sfe_bus_rd_pxls_to_bytes(uint32_t pxls, uint32_t fmt,
@@ -1411,7 +1412,7 @@ static int cam_sfe_bus_rd_config_rm(void *priv, void *cmd_args,
 		rm_data->height = height;
 		rm_data->width = width;
 		curr_cache_cfg = rm_data->cache_cfg;
-		rm_data->cache_cfg = 0x20;
+		rm_data->cache_cfg = bus_priv->sys_cache_default_cfg;
 		if ((!cache_dbg_cfg->disable_for_scratch) &&
 			(rm_data->enable_caching)) {
 			rm_data->cache_cfg =
@@ -1562,7 +1563,7 @@ static int cam_sfe_bus_rd_update_rm(void *priv, void *cmd_args,
 		rm_data->width = width;
 
 		curr_cache_cfg = rm_data->cache_cfg;
-		rm_data->cache_cfg = 0x20;
+		rm_data->cache_cfg = bus_priv->sys_cache_default_cfg;
 		if (rm_data->enable_caching) {
 			if ((cache_dbg_cfg->disable_for_scratch) &&
 				(update_buf->use_scratch_cfg))
@@ -2030,6 +2031,7 @@ int cam_sfe_bus_rd_init(
 		bus_rd_hw_info->constraint_error_info->cons_chk_en_avail;
 	bus_priv->top_irq_shift                 = bus_rd_hw_info->top_irq_shift;
 	bus_priv->latency_buf_allocation        = bus_rd_hw_info->latency_buf_allocation;
+	bus_priv->sys_cache_default_cfg         = bus_rd_hw_info->sys_cache_default_val;
 	bus_priv->bus_rd_hw_info = bus_rd_hw_info;
 
 	rc = cam_irq_controller_init(drv_name,

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.h

@@ -120,6 +120,7 @@ struct cam_sfe_bus_rd_info {
  * @sfe_bus_rd_info:        SFE bus rd client info
  * @top_irq_shift:          Top irq shift val
  * @latency_buf_allocation: latency buf allocation
+ * @sys_cache_default_val:  System cache default config
  * @irq_err_mask:           IRQ error mask
  * @fs_sync_shift:          Shift to enable FS sync
  * @constraint_error_info:  constraint violation errors info
@@ -134,6 +135,7 @@ struct cam_sfe_bus_rd_hw_info {
 		sfe_bus_rd_info[CAM_SFE_BUS_RD_MAX];
 	uint32_t top_irq_shift;
 	uint32_t latency_buf_allocation;
+	uint32_t sys_cache_default_val;
 	uint32_t irq_err_mask;
 	uint32_t fs_sync_shift;
 	struct cam_sfe_bus_rd_constraint_error_info *constraint_error_info;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -91,6 +91,7 @@ struct cam_sfe_bus_wr_common_data {
 	cam_hw_mgr_event_cb_func                    event_cb;
 	uint32_t                                    irq_err_mask;
 
+	uint32_t                                    sys_cache_default_cfg;
 	uint32_t                                    sfe_debug_cfg;
 	struct cam_sfe_bus_cache_dbg_cfg            cache_dbg_cfg;
 };
@@ -2539,7 +2540,7 @@ static int cam_sfe_bus_wr_update_wm(void *priv, void *cmd_args,
 			reg_val_pair[j-1]);
 
 		curr_cache_cfg = wm_data->cache_cfg;
-		wm_data->cache_cfg = 0;
+		wm_data->cache_cfg = bus_priv->common_data.sys_cache_default_cfg;
 		if (wm_data->enable_caching) {
 			if ((cache_dbg_cfg->disable_for_scratch) &&
 				(update_buf->use_scratch_cfg))
@@ -2799,7 +2800,7 @@ static int cam_sfe_bus_wr_config_wm(void *priv, void *cmd_args,
 			CAM_BOOL_TO_YESNO(cam_smmu_is_expanded_memory));
 
 		curr_cache_cfg = wm_data->cache_cfg;
-		wm_data->cache_cfg = 0;
+		wm_data->cache_cfg = bus_priv->common_data.sys_cache_default_cfg;
 		if ((!cache_dbg_cfg->disable_for_scratch) &&
 			(wm_data->enable_caching)) {
 			wm_data->cache_cfg =
@@ -3500,6 +3501,7 @@ int cam_sfe_bus_wr_init(
 	bus_priv->common_data.err_irq_subscribe    = false;
 	bus_priv->common_data.sfe_irq_controller   = sfe_irq_controller;
 	bus_priv->common_data.irq_err_mask         = hw_info->irq_err_mask;
+	bus_priv->common_data.sys_cache_default_cfg = hw_info->sys_cache_default_val;
 	bus_priv->constraint_error_info            = hw_info->constraint_error_info;
 	bus_priv->sfe_out_hw_info                  = hw_info->sfe_out_hw_info;
 	rc = cam_cpas_get_cpas_hw_version(&bus_priv->common_data.hw_version);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -185,6 +185,7 @@ struct cam_sfe_bus_sfe_out_hw_info {
  * @max_out_res:               maximum number of sfe out res in uapi
  * @pack_align_shift:          Packer format alignment bit shift
  * @max_bw_counter_limit:      Max BW counter limit
+ * @sys_cache_default_val:     System cache default config
  * @irq_err_mask:              IRQ error mask
  */
 struct cam_sfe_bus_wr_hw_info {
@@ -204,6 +205,7 @@ struct cam_sfe_bus_wr_hw_info {
 	uint32_t max_out_res;
 	uint32_t pack_align_shift;
 	uint32_t max_bw_counter_limit;
+	uint32_t sys_cache_default_val;
 	uint32_t irq_err_mask;
 };