disp: inc: uapi: fix UAPI headers to compile with UAPI_HEADER_TEST
Fix headers so that they compile with UAPI_HEADER_TEST. Change-Id: I2585a18b02abcc3a52ec0079aa4cc1ce55ee1b56 Signed-off-by: Steve Cohen <cohens@codeaurora.org>
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Steve Cohen
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@@ -137,25 +137,25 @@ struct sde_drm_pix_ext_v1 {
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* Number of pixels ext in left, right, top and bottom direction
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* for all color components.
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*/
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int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
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int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
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__s32 num_ext_pxls_lr[SDE_MAX_PLANES];
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__s32 num_ext_pxls_tb[SDE_MAX_PLANES];
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/*
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* Number of pixels needs to be overfetched in left, right, top
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* and bottom directions from source image for scaling.
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*/
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int32_t left_ftch[SDE_MAX_PLANES];
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int32_t right_ftch[SDE_MAX_PLANES];
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int32_t top_ftch[SDE_MAX_PLANES];
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int32_t btm_ftch[SDE_MAX_PLANES];
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__s32 left_ftch[SDE_MAX_PLANES];
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__s32 right_ftch[SDE_MAX_PLANES];
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__s32 top_ftch[SDE_MAX_PLANES];
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__s32 btm_ftch[SDE_MAX_PLANES];
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/*
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* Number of pixels needs to be repeated in left, right, top and
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* bottom directions for scaling.
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*/
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int32_t left_rpt[SDE_MAX_PLANES];
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int32_t right_rpt[SDE_MAX_PLANES];
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int32_t top_rpt[SDE_MAX_PLANES];
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int32_t btm_rpt[SDE_MAX_PLANES];
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__s32 left_rpt[SDE_MAX_PLANES];
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__s32 right_rpt[SDE_MAX_PLANES];
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__s32 top_rpt[SDE_MAX_PLANES];
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__s32 btm_rpt[SDE_MAX_PLANES];
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};
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@@ -178,17 +178,17 @@ struct sde_drm_scaler_v1 {
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/*
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* Phase settings
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*/
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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__s32 init_phase_x[SDE_MAX_PLANES];
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__s32 phase_step_x[SDE_MAX_PLANES];
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__s32 init_phase_y[SDE_MAX_PLANES];
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__s32 phase_step_y[SDE_MAX_PLANES];
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/*
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* Filter type to be used for scaling in horizontal and vertical
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* directions
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*/
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uint32_t horz_filter[SDE_MAX_PLANES];
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uint32_t vert_filter[SDE_MAX_PLANES];
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__u32 horz_filter[SDE_MAX_PLANES];
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__u32 vert_filter[SDE_MAX_PLANES];
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};
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/**
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@@ -208,19 +208,19 @@ struct sde_drm_scaler_v1 {
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* @adjust_c: Mapping curves C coefficients
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*/
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struct sde_drm_de_v1 {
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uint32_t enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[SDE_MAX_DE_CURVES];
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int16_t adjust_b[SDE_MAX_DE_CURVES];
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int16_t adjust_c[SDE_MAX_DE_CURVES];
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__u32 enable;
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__s16 sharpen_level1;
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__s16 sharpen_level2;
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__u16 clip;
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__u16 limit;
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__u16 thr_quiet;
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__u16 thr_dieout;
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__u16 thr_low;
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__u16 thr_high;
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__u16 prec_shift;
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__s16 adjust_a[SDE_MAX_DE_CURVES];
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__s16 adjust_b[SDE_MAX_DE_CURVES];
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__s16 adjust_c[SDE_MAX_DE_CURVES];
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};
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/*
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@@ -275,8 +275,8 @@ struct sde_drm_scaler_v2 {
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/*
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* General definitions
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*/
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uint32_t enable;
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uint32_t dir_en;
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__u32 enable;
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__u32 dir_en;
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/*
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* Pix ext settings
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@@ -286,55 +286,55 @@ struct sde_drm_scaler_v2 {
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/*
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* Decimation settings
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*/
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uint32_t horz_decimate;
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uint32_t vert_decimate;
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__u32 horz_decimate;
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__u32 vert_decimate;
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/*
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* Phase settings
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*/
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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__s32 init_phase_x[SDE_MAX_PLANES];
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__s32 phase_step_x[SDE_MAX_PLANES];
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__s32 init_phase_y[SDE_MAX_PLANES];
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__s32 phase_step_y[SDE_MAX_PLANES];
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uint32_t preload_x[SDE_MAX_PLANES];
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uint32_t preload_y[SDE_MAX_PLANES];
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uint32_t src_width[SDE_MAX_PLANES];
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uint32_t src_height[SDE_MAX_PLANES];
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__u32 preload_x[SDE_MAX_PLANES];
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__u32 preload_y[SDE_MAX_PLANES];
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__u32 src_width[SDE_MAX_PLANES];
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__u32 src_height[SDE_MAX_PLANES];
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uint32_t dst_width;
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uint32_t dst_height;
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__u32 dst_width;
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__u32 dst_height;
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uint32_t y_rgb_filter_cfg;
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uint32_t uv_filter_cfg;
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uint32_t alpha_filter_cfg;
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uint32_t blend_cfg;
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__u32 y_rgb_filter_cfg;
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__u32 uv_filter_cfg;
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__u32 alpha_filter_cfg;
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__u32 blend_cfg;
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uint32_t lut_flag;
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uint32_t dir_lut_idx;
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__u32 lut_flag;
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__u32 dir_lut_idx;
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/* for Y(RGB) and UV planes*/
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uint32_t y_rgb_cir_lut_idx;
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uint32_t uv_cir_lut_idx;
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uint32_t y_rgb_sep_lut_idx;
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uint32_t uv_sep_lut_idx;
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__u32 y_rgb_cir_lut_idx;
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__u32 uv_cir_lut_idx;
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__u32 y_rgb_sep_lut_idx;
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__u32 uv_sep_lut_idx;
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/*
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* Detail enhancer settings
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*/
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struct sde_drm_de_v1 de;
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uint32_t dir_weight;
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uint32_t unsharp_mask_blend;
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uint32_t de_blend;
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uint32_t flags;
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__u32 dir_weight;
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__u32 unsharp_mask_blend;
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__u32 de_blend;
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__u32 flags;
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/*
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* Inline pre-downscale settings
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*/
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uint32_t pre_downscale_x_0;
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uint32_t pre_downscale_x_1;
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uint32_t pre_downscale_y_0;
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uint32_t pre_downscale_y_1;
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__u32 pre_downscale_x_0;
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__u32 pre_downscale_x_1;
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__u32 pre_downscale_y_0;
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__u32 pre_downscale_y_1;
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};
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/* Number of dest scalers supported */
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@@ -359,11 +359,11 @@ struct sde_drm_scaler_v2 {
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* Userspace pointer to struct sde_drm_scaler_v2
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*/
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struct sde_drm_dest_scaler_cfg {
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uint32_t flags;
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uint32_t index;
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uint32_t lm_width;
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uint32_t lm_height;
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uint64_t scaler_cfg;
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__u32 flags;
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__u32 index;
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__u32 lm_width;
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__u32 lm_height;
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__u64 scaler_cfg;
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};
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/**
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@@ -372,7 +372,7 @@ struct sde_drm_dest_scaler_cfg {
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* @ds_cfg: Destination scaler block configuration
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*/
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struct sde_drm_dest_scaler_data {
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uint32_t num_dest_scaler;
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__u32 num_dest_scaler;
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struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
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};
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@@ -392,11 +392,11 @@ struct sde_drm_dest_scaler_data {
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* @post_clamp: Post-clamp array values
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*/
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struct sde_drm_csc_v1 {
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int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
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uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
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uint32_t post_bias[SDE_CSC_BIAS_SIZE];
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uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
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uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
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__s64 ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
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__u32 pre_bias[SDE_CSC_BIAS_SIZE];
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__u32 post_bias[SDE_CSC_BIAS_SIZE];
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__u32 pre_clamp[SDE_CSC_CLAMP_SIZE];
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__u32 post_clamp[SDE_CSC_CLAMP_SIZE];
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};
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/**
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@@ -407,10 +407,10 @@ struct sde_drm_csc_v1 {
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* @color_3: Color 3 value
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*/
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struct sde_drm_color {
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uint32_t color_0;
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uint32_t color_1;
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uint32_t color_2;
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uint32_t color_3;
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__u32 color_0;
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__u32 color_1;
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__u32 color_2;
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__u32 color_3;
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};
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/* Total number of supported dim layers */
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@@ -430,8 +430,8 @@ struct sde_drm_color {
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* @rect: Dim layer coordinates
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*/
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struct sde_drm_dim_layer_cfg {
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uint32_t flags;
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uint32_t stage;
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__u32 flags;
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__u32 stage;
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struct sde_drm_color color_fill;
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struct drm_clip_rect rect;
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};
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@@ -442,7 +442,7 @@ struct sde_drm_dim_layer_cfg {
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* @layer: Dim layer user cfgs ptr for the num_layers
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*/
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struct sde_drm_dim_layer_v1 {
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uint32_t num_layers;
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__u32 num_layers;
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struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
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};
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@@ -460,10 +460,10 @@ struct sde_drm_dim_layer_v1 {
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* @modes: Pointer to struct drm_mode_modeinfo
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*/
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struct sde_drm_wb_cfg {
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uint32_t flags;
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uint32_t connector_id;
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uint32_t count_modes;
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uint64_t modes;
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__u32 flags;
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__u32 connector_id;
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__u32 count_modes;
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__u64 modes;
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};
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#define SDE_MAX_ROI_V1 4
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@@ -474,7 +474,7 @@ struct sde_drm_wb_cfg {
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* @roi: list of roi rectangles
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*/
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struct sde_drm_roi_v1 {
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uint32_t num_rects;
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__u32 num_rects;
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struct drm_clip_rect roi[SDE_MAX_ROI_V1];
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};
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@@ -6,6 +6,8 @@
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#ifndef _UAPI__MSM_HDMI_HDCP_MGR_H
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#define _UAPI__MSM_HDMI_HDCP_MGR_H
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#include <linux/types.h>
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enum DS_TYPE { /* type of downstream device */
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DS_UNKNOWN,
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DS_RECEIVER,
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@@ -47,13 +49,13 @@ enum SOURCE_ID {
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struct HDCP_V2V1_MSG_TOPOLOGY {
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/* indicates downstream's type */
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uint32_t ds_type;
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uint8_t bksv[5];
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uint8_t dev_count;
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uint8_t depth;
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uint8_t ksv_list[5 * 127];
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uint32_t max_cascade_exceeded;
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uint32_t max_dev_exceeded;
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__u32 ds_type;
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__u8 bksv[5];
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__u8 dev_count;
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__u8 depth;
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__u8 ksv_list[5 * 127];
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__u32 max_cascade_exceeded;
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__u32 max_dev_exceeded;
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};
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#endif /* _UAPI__MSM_HDMI_HDCP_MGR_H */
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