qcacmn: Add hal_rx_msdu_end_da_is_mcbc_get API

Implement hal_rx_msdu_end_da_is_mcbc_get based
on the chipset as the macro to retrieve
mcbc value is chipset dependent.

Change-Id: I860d259515c31345501080577d7a34beb97e5f60
CRs-Fixed: 2522133
This commit is contained in:
Venkata Sharath Chandra Manchala
2019-09-20 10:52:37 -07:00
gecommit door nshrivas
bovenliggende d1b7e4c326
commit ee90938f62
15 gewijzigde bestanden met toevoegingen van 153 en 27 verwijderingen

Bestand weergeven

@@ -2023,7 +2023,8 @@ done:
if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) { if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
bool is_mcbc, is_sa_vld, is_da_vld; bool is_mcbc, is_sa_vld, is_da_vld;
is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr); is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
rx_tlv_hdr);
is_sa_vld = hal_rx_msdu_end_sa_is_valid_get(rx_tlv_hdr); is_sa_vld = hal_rx_msdu_end_sa_is_valid_get(rx_tlv_hdr);
is_da_vld = hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr); is_da_vld = hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr);

Bestand weergeven

@@ -64,7 +64,7 @@ static inline bool dp_rx_mcast_echo_check(struct dp_soc *soc,
if (vdev->opmode != wlan_op_mode_sta) if (vdev->opmode != wlan_op_mode_sta)
return false; return false;
if (!hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr)) if (!hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc, rx_tlv_hdr))
return false; return false;
data = qdf_nbuf_data(nbuf); data = qdf_nbuf_data(nbuf);
@@ -700,7 +700,8 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
hal_rx_msdu_end_first_msdu_get(rx_tlv_hdr)); hal_rx_msdu_end_first_msdu_get(rx_tlv_hdr));
qdf_nbuf_set_rx_chfrag_end(nbuf, qdf_nbuf_set_rx_chfrag_end(nbuf,
hal_rx_msdu_end_last_msdu_get(rx_tlv_hdr)); hal_rx_msdu_end_last_msdu_get(rx_tlv_hdr));
qdf_nbuf_set_da_mcbc(nbuf, hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr)); qdf_nbuf_set_da_mcbc(nbuf, hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
rx_tlv_hdr));
qdf_nbuf_set_da_valid(nbuf, qdf_nbuf_set_da_valid(nbuf,
hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr)); hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr));
qdf_nbuf_set_sa_valid(nbuf, qdf_nbuf_set_sa_valid(nbuf,
@@ -792,7 +793,8 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
if (qdf_unlikely((peer->nawds_enabled == true) && if (qdf_unlikely((peer->nawds_enabled == true) &&
hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr))) { hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
rx_tlv_hdr))) {
dp_err_rl("free buffer for multicast packet"); dp_err_rl("free buffer for multicast packet");
DP_STATS_INC(peer, rx.nawds_mcast_drop, 1); DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
goto drop_nbuf; goto drop_nbuf;
@@ -836,7 +838,7 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
rx_tlv_hdr, true); rx_tlv_hdr, true);
if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get( if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(
rx_tlv_hdr) && soc->hal_soc, rx_tlv_hdr) &&
(vdev->rx_decap_type == (vdev->rx_decap_type ==
htt_cmn_pkt_type_ethernet))) { htt_cmn_pkt_type_ethernet))) {
eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf); eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
@@ -995,8 +997,9 @@ process_mesh:
dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer); dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
} }
process_rx: process_rx:
if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr) && if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
(vdev->rx_decap_type == rx_tlv_hdr) &&
(vdev->rx_decap_type ==
htt_cmn_pkt_type_ethernet))) { htt_cmn_pkt_type_ethernet))) {
eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf); eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
is_broadcast = (QDF_IS_ADDR_BROADCAST is_broadcast = (QDF_IS_ADDR_BROADCAST

Bestand weergeven

@@ -381,6 +381,7 @@ struct hal_hw_txrx_ops {
uint8_t id); uint8_t id);
void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
}; };
/** /**

Bestand weergeven

@@ -1848,29 +1848,20 @@ hal_rx_msdu_end_da_is_valid_get(uint8_t *buf)
return da_is_valid; return da_is_valid;
} }
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ /**
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
RX_MSDU_END_5_DA_IS_MCBC_LSB))
/**
* hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
* from rx_msdu_end TLV * from rx_msdu_end TLV
* *
* @ buf: pointer to the start of RX PKT TLV headers * @buf: pointer to the start of RX PKT TLV headers
*
* Return: da_is_mcbc * Return: da_is_mcbc
*/ */
static inline uint8_t static inline uint8_t
hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf) hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
{ {
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint8_t da_is_mcbc;
da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
return da_is_mcbc;
} }
#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \

Bestand weergeven

@@ -127,6 +127,22 @@ uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf)
DOT11_SEQ_FRAG_MASK); DOT11_SEQ_FRAG_MASK);
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
* from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static inline uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -169,6 +185,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
hal_tx_update_pcp_tid_generic, hal_tx_update_pcp_tid_generic,
hal_tx_update_tidmap_prty_generic, hal_tx_update_tidmap_prty_generic,
hal_rx_get_rx_fragment_number_6290, hal_rx_get_rx_fragment_number_6290,
hal_rx_msdu_end_da_is_mcbc_get_6290,
}; };
struct hal_hw_srng_config hw_srng_table_6290[] = { struct hal_hw_srng_config hw_srng_table_6290[] = {
@@ -620,4 +637,3 @@ void hal_qca6290_attach(struct hal_soc *hal_soc)
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290; hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290;
hal_soc->ops = &qca6290_hal_hw_txrx_ops; hal_soc->ops = &qca6290_hal_hw_txrx_ops;
} }

Bestand weergeven

@@ -41,6 +41,12 @@
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
RX_MSDU_END_5_DA_IS_MCBC_LSB))
#if defined(QCA_WIFI_QCA6290_11AX) #if defined(QCA_WIFI_QCA6290_11AX)
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\

Bestand weergeven

@@ -127,6 +127,22 @@ uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf)
DOT11_SEQ_FRAG_MASK); DOT11_SEQ_FRAG_MASK);
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC
* from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
hal_srng_dst_hw_init_generic, hal_srng_dst_hw_init_generic,
@@ -169,6 +185,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
hal_tx_update_pcp_tid_generic, hal_tx_update_pcp_tid_generic,
hal_tx_update_tidmap_prty_generic, hal_tx_update_tidmap_prty_generic,
hal_rx_get_rx_fragment_number_6390, hal_rx_get_rx_fragment_number_6390,
hal_rx_msdu_end_da_is_mcbc_get_6390,
}; };
struct hal_hw_srng_config hw_srng_table_6390[] = { struct hal_hw_srng_config hw_srng_table_6390[] = {
@@ -624,4 +641,3 @@ void hal_qca6390_attach(struct hal_soc *hal_soc)
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390; hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
hal_soc->ops = &qca6390_hal_hw_txrx_ops; hal_soc->ops = &qca6390_hal_hw_txrx_ops;
} }

Bestand weergeven

@@ -41,6 +41,12 @@
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
RX_MSDU_END_5_DA_IS_MCBC_LSB))
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \

Bestand weergeven

@@ -33,7 +33,24 @@ uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf)
DOT11_SEQ_FRAG_MASK); DOT11_SEQ_FRAG_MASK);
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC
* from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
/* rx */ /* rx */
hal_rx_get_rx_fragment_number_6490, hal_rx_get_rx_fragment_number_6490,
hal_rx_msdu_end_da_is_mcbc_get_6490,
}; };

Bestand weergeven

@@ -21,3 +21,9 @@
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_10_DA_IS_MCBC_MASK, \
RX_MSDU_END_10_DA_IS_MCBC_LSB))

Bestand weergeven

@@ -123,6 +123,22 @@ uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf)
DOT11_SEQ_FRAG_MASK); DOT11_SEQ_FRAG_MASK);
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if
* pkt is MCBC from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -166,6 +182,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
hal_tx_update_pcp_tid_generic, hal_tx_update_pcp_tid_generic,
hal_tx_update_tidmap_prty_generic, hal_tx_update_tidmap_prty_generic,
hal_rx_get_rx_fragment_number_8074v1, hal_rx_get_rx_fragment_number_8074v1,
hal_rx_msdu_end_da_is_mcbc_get_8074v1,
}; };
struct hal_hw_srng_config hw_srng_table_8074[] = { struct hal_hw_srng_config hw_srng_table_8074[] = {
@@ -620,4 +637,3 @@ void hal_qca8074_attach(struct hal_soc *hal_soc)
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074; hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074;
hal_soc->ops = &qca8074_hal_hw_txrx_ops; hal_soc->ops = &qca8074_hal_hw_txrx_ops;
} }

Bestand weergeven

@@ -29,6 +29,13 @@
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \ RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
RX_MSDU_END_5_DA_IS_MCBC_LSB))
/* /*
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS * hal_rx_msdu_start_nss_get_8074(): API to get the NSS
* Interval from rx_msdu_start * Interval from rx_msdu_start

Bestand weergeven

@@ -122,6 +122,23 @@ uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf)
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
DOT11_SEQ_FRAG_MASK; DOT11_SEQ_FRAG_MASK;
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC
* from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -165,6 +182,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
hal_tx_update_pcp_tid_generic, hal_tx_update_pcp_tid_generic,
hal_tx_update_tidmap_prty_generic, hal_tx_update_tidmap_prty_generic,
hal_rx_get_rx_fragment_number_8074v2, hal_rx_get_rx_fragment_number_8074v2,
hal_rx_msdu_end_da_is_mcbc_get_8074v2,
}; };
struct hal_hw_srng_config hw_srng_table_8074v2[] = { struct hal_hw_srng_config hw_srng_table_8074v2[] = {
@@ -621,4 +639,3 @@ void hal_qca8074v2_attach(struct hal_soc *hal_soc)
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2; hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
hal_soc->ops = &qca8074v2_hal_hw_txrx_ops; hal_soc->ops = &qca8074v2_hal_hw_txrx_ops;
} }

Bestand weergeven

@@ -33,6 +33,12 @@
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \ RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB)) RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
RX_MSDU_END_5_DA_IS_MCBC_LSB))
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \

Bestand weergeven

@@ -131,6 +131,23 @@ uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf)
return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
DOT11_SEQ_FRAG_MASK); DOT11_SEQ_FRAG_MASK);
} }
/**
* hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC
* from rx_msdu_end TLV
*
* @ buf: pointer to the start of RX PKT TLV headers
* Return: da_is_mcbc
*/
static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
}
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = { struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
/* init and setup */ /* init and setup */
@@ -174,6 +191,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
hal_tx_update_pcp_tid_generic, hal_tx_update_pcp_tid_generic,
hal_tx_update_tidmap_prty_generic, hal_tx_update_tidmap_prty_generic,
hal_rx_get_rx_fragment_number_9000, hal_rx_get_rx_fragment_number_9000,
hal_rx_msdu_end_da_is_mcbc_get_9000,
}; };
struct hal_hw_srng_config hw_srng_table_9000[] = { struct hal_hw_srng_config hw_srng_table_9000[] = {
@@ -631,4 +649,3 @@ void hal_qcn9000_attach(struct hal_soc *hal_soc)
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000; hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000;
hal_soc->ops = &qcn9000_hal_hw_txrx_ops; hal_soc->ops = &qcn9000_hal_hw_txrx_ops;
} }