qcacmn: Add hal_rx_msdu_end_da_is_mcbc_get API
Implement hal_rx_msdu_end_da_is_mcbc_get based on the chipset as the macro to retrieve mcbc value is chipset dependent. Change-Id: I860d259515c31345501080577d7a34beb97e5f60 CRs-Fixed: 2522133
This commit is contained in:

gecommit door
nshrivas

bovenliggende
d1b7e4c326
commit
ee90938f62
@@ -2023,7 +2023,8 @@ done:
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if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
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if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
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bool is_mcbc, is_sa_vld, is_da_vld;
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bool is_mcbc, is_sa_vld, is_da_vld;
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is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr);
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is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
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rx_tlv_hdr);
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is_sa_vld = hal_rx_msdu_end_sa_is_valid_get(rx_tlv_hdr);
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is_sa_vld = hal_rx_msdu_end_sa_is_valid_get(rx_tlv_hdr);
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is_da_vld = hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr);
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is_da_vld = hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr);
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@@ -64,7 +64,7 @@ static inline bool dp_rx_mcast_echo_check(struct dp_soc *soc,
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if (vdev->opmode != wlan_op_mode_sta)
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if (vdev->opmode != wlan_op_mode_sta)
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return false;
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return false;
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if (!hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr))
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if (!hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc, rx_tlv_hdr))
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return false;
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return false;
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data = qdf_nbuf_data(nbuf);
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data = qdf_nbuf_data(nbuf);
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@@ -700,7 +700,8 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
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hal_rx_msdu_end_first_msdu_get(rx_tlv_hdr));
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hal_rx_msdu_end_first_msdu_get(rx_tlv_hdr));
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qdf_nbuf_set_rx_chfrag_end(nbuf,
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qdf_nbuf_set_rx_chfrag_end(nbuf,
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hal_rx_msdu_end_last_msdu_get(rx_tlv_hdr));
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hal_rx_msdu_end_last_msdu_get(rx_tlv_hdr));
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qdf_nbuf_set_da_mcbc(nbuf, hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr));
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qdf_nbuf_set_da_mcbc(nbuf, hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
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rx_tlv_hdr));
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qdf_nbuf_set_da_valid(nbuf,
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qdf_nbuf_set_da_valid(nbuf,
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hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr));
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hal_rx_msdu_end_da_is_valid_get(rx_tlv_hdr));
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qdf_nbuf_set_sa_valid(nbuf,
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qdf_nbuf_set_sa_valid(nbuf,
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@@ -792,7 +793,8 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
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if (qdf_unlikely((peer->nawds_enabled == true) &&
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if (qdf_unlikely((peer->nawds_enabled == true) &&
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hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr))) {
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hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
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rx_tlv_hdr))) {
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dp_err_rl("free buffer for multicast packet");
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dp_err_rl("free buffer for multicast packet");
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DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
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DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
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goto drop_nbuf;
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goto drop_nbuf;
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@@ -836,7 +838,7 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
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rx_tlv_hdr, true);
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rx_tlv_hdr, true);
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if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(
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if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(
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rx_tlv_hdr) &&
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soc->hal_soc, rx_tlv_hdr) &&
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(vdev->rx_decap_type ==
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(vdev->rx_decap_type ==
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htt_cmn_pkt_type_ethernet))) {
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htt_cmn_pkt_type_ethernet))) {
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eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
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eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
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@@ -995,8 +997,9 @@ process_mesh:
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dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
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dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
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}
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}
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process_rx:
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process_rx:
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if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(rx_tlv_hdr) &&
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if (qdf_unlikely(hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
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(vdev->rx_decap_type ==
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rx_tlv_hdr) &&
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(vdev->rx_decap_type ==
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htt_cmn_pkt_type_ethernet))) {
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htt_cmn_pkt_type_ethernet))) {
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eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
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eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
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is_broadcast = (QDF_IS_ADDR_BROADCAST
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is_broadcast = (QDF_IS_ADDR_BROADCAST
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@@ -381,6 +381,7 @@ struct hal_hw_txrx_ops {
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uint8_t id);
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uint8_t id);
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void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
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void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
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uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
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uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
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};
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};
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/**
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/**
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@@ -1848,29 +1848,20 @@ hal_rx_msdu_end_da_is_valid_get(uint8_t *buf)
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return da_is_valid;
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return da_is_valid;
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}
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}
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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/**
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_5_DA_IS_MCBC_MASK, \
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RX_MSDU_END_5_DA_IS_MCBC_LSB))
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/**
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* hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
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* hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
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* from rx_msdu_end TLV
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* from rx_msdu_end TLV
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*
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*
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* @ buf: pointer to the start of RX PKT TLV headers
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* @buf: pointer to the start of RX PKT TLV headers
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*
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* Return: da_is_mcbc
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* Return: da_is_mcbc
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*/
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*/
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static inline uint8_t
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static inline uint8_t
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hal_rx_msdu_end_da_is_mcbc_get(uint8_t *buf)
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hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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{
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
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uint8_t da_is_mcbc;
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da_is_mcbc = HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
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return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
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return da_is_mcbc;
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}
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}
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#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
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#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
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@@ -127,6 +127,22 @@ uint8_t hal_rx_get_rx_fragment_number_6290(uint8_t *buf)
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DOT11_SEQ_FRAG_MASK);
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DOT11_SEQ_FRAG_MASK);
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}
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}
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/**
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* hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
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* from rx_msdu_end TLV
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*
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* @ buf: pointer to the start of RX PKT TLV headers
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* Return: da_is_mcbc
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*/
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static inline uint8_t
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hal_rx_msdu_end_da_is_mcbc_get_6290(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
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}
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -169,6 +185,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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hal_tx_update_pcp_tid_generic,
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hal_tx_update_pcp_tid_generic,
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hal_tx_update_tidmap_prty_generic,
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hal_tx_update_tidmap_prty_generic,
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hal_rx_get_rx_fragment_number_6290,
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hal_rx_get_rx_fragment_number_6290,
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hal_rx_msdu_end_da_is_mcbc_get_6290,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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@@ -620,4 +637,3 @@ void hal_qca6290_attach(struct hal_soc *hal_soc)
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hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290;
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hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290;
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hal_soc->ops = &qca6290_hal_hw_txrx_ops;
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hal_soc->ops = &qca6290_hal_hw_txrx_ops;
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}
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}
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@@ -41,6 +41,12 @@
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_5_DA_IS_MCBC_MASK, \
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RX_MSDU_END_5_DA_IS_MCBC_LSB))
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#if defined(QCA_WIFI_QCA6290_11AX)
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#if defined(QCA_WIFI_QCA6290_11AX)
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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@@ -127,6 +127,22 @@ uint8_t hal_rx_get_rx_fragment_number_6390(uint8_t *buf)
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DOT11_SEQ_FRAG_MASK);
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DOT11_SEQ_FRAG_MASK);
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}
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}
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/**
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* hal_rx_msdu_end_da_is_mcbc_get_6390(): API to check if pkt is MCBC
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* from rx_msdu_end TLV
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*
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* @ buf: pointer to the start of RX PKT TLV headers
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* Return: da_is_mcbc
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*/
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static uint8_t
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hal_rx_msdu_end_da_is_mcbc_get_6390(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
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}
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -169,6 +185,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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hal_tx_update_pcp_tid_generic,
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hal_tx_update_pcp_tid_generic,
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hal_tx_update_tidmap_prty_generic,
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hal_tx_update_tidmap_prty_generic,
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hal_rx_get_rx_fragment_number_6390,
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hal_rx_get_rx_fragment_number_6390,
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hal_rx_msdu_end_da_is_mcbc_get_6390,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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@@ -624,4 +641,3 @@ void hal_qca6390_attach(struct hal_soc *hal_soc)
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hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
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hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
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hal_soc->ops = &qca6390_hal_hw_txrx_ops;
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hal_soc->ops = &qca6390_hal_hw_txrx_ops;
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}
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}
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@@ -41,6 +41,12 @@
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
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RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_5_DA_IS_MCBC_MASK, \
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RX_MSDU_END_5_DA_IS_MCBC_LSB))
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
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RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
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@@ -33,7 +33,24 @@ uint8_t hal_rx_get_rx_fragment_number_6490(uint8_t *buf)
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DOT11_SEQ_FRAG_MASK);
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DOT11_SEQ_FRAG_MASK);
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}
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}
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/**
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* hal_rx_msdu_end_da_is_mcbc_get_6490(): API to check if pkt is MCBC
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* from rx_msdu_end TLV
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*
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* @ buf: pointer to the start of RX PKT TLV headers
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* Return: da_is_mcbc
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*/
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static uint8_t
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hal_rx_msdu_end_da_is_mcbc_get_6490(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
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return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
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}
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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/* rx */
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/* rx */
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hal_rx_get_rx_fragment_number_6490,
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hal_rx_get_rx_fragment_number_6490,
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hal_rx_msdu_end_da_is_mcbc_get_6490,
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};
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};
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@@ -21,3 +21,9 @@
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_10_DA_IS_MCBC_MASK, \
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RX_MSDU_END_10_DA_IS_MCBC_LSB))
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@@ -123,6 +123,22 @@ uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf)
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DOT11_SEQ_FRAG_MASK);
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DOT11_SEQ_FRAG_MASK);
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}
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}
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||||||
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|
||||||
|
/**
|
||||||
|
* hal_rx_msdu_end_da_is_mcbc_get_8074v1(): API to check if
|
||||||
|
* pkt is MCBC from rx_msdu_end TLV
|
||||||
|
*
|
||||||
|
* @ buf: pointer to the start of RX PKT TLV headers
|
||||||
|
* Return: da_is_mcbc
|
||||||
|
*/
|
||||||
|
static uint8_t
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf)
|
||||||
|
{
|
||||||
|
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
|
||||||
|
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
|
||||||
|
|
||||||
|
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -166,6 +182,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
|||||||
hal_tx_update_pcp_tid_generic,
|
hal_tx_update_pcp_tid_generic,
|
||||||
hal_tx_update_tidmap_prty_generic,
|
hal_tx_update_tidmap_prty_generic,
|
||||||
hal_rx_get_rx_fragment_number_8074v1,
|
hal_rx_get_rx_fragment_number_8074v1,
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_8074v1,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_8074[] = {
|
struct hal_hw_srng_config hw_srng_table_8074[] = {
|
||||||
@@ -620,4 +637,3 @@ void hal_qca8074_attach(struct hal_soc *hal_soc)
|
|||||||
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074;
|
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074;
|
||||||
hal_soc->ops = &qca8074_hal_hw_txrx_ops;
|
hal_soc->ops = &qca8074_hal_hw_txrx_ops;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -29,6 +29,13 @@
|
|||||||
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
|
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
|
||||||
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
|
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
|
||||||
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
|
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
|
||||||
|
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_LSB))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS
|
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS
|
||||||
* Interval from rx_msdu_start
|
* Interval from rx_msdu_start
|
||||||
|
@@ -122,6 +122,23 @@ uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf)
|
|||||||
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
|
return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
|
||||||
DOT11_SEQ_FRAG_MASK;
|
DOT11_SEQ_FRAG_MASK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_rx_msdu_end_da_is_mcbc_get_8074v2: API to check if pkt is MCBC
|
||||||
|
* from rx_msdu_end TLV
|
||||||
|
*
|
||||||
|
* @ buf: pointer to the start of RX PKT TLV headers
|
||||||
|
* Return: da_is_mcbc
|
||||||
|
*/
|
||||||
|
static uint8_t
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf)
|
||||||
|
{
|
||||||
|
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
|
||||||
|
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
|
||||||
|
|
||||||
|
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -165,6 +182,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
|||||||
hal_tx_update_pcp_tid_generic,
|
hal_tx_update_pcp_tid_generic,
|
||||||
hal_tx_update_tidmap_prty_generic,
|
hal_tx_update_tidmap_prty_generic,
|
||||||
hal_rx_get_rx_fragment_number_8074v2,
|
hal_rx_get_rx_fragment_number_8074v2,
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_8074v2,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
|
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
|
||||||
@@ -621,4 +639,3 @@ void hal_qca8074v2_attach(struct hal_soc *hal_soc)
|
|||||||
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
|
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
|
||||||
hal_soc->ops = &qca8074v2_hal_hw_txrx_ops;
|
hal_soc->ops = &qca8074v2_hal_hw_txrx_ops;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -33,6 +33,12 @@
|
|||||||
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
|
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
|
||||||
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
|
RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
|
||||||
|
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_MASK, \
|
||||||
|
RX_MSDU_END_5_DA_IS_MCBC_LSB))
|
||||||
|
|
||||||
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
|
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
|
||||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
|
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
|
||||||
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
|
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
|
||||||
|
@@ -131,6 +131,23 @@ uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf)
|
|||||||
return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
|
return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
|
||||||
DOT11_SEQ_FRAG_MASK);
|
DOT11_SEQ_FRAG_MASK);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_rx_msdu_end_da_is_mcbc_get_9000(): API to check if pkt is MCBC
|
||||||
|
* from rx_msdu_end TLV
|
||||||
|
*
|
||||||
|
* @ buf: pointer to the start of RX PKT TLV headers
|
||||||
|
* Return: da_is_mcbc
|
||||||
|
*/
|
||||||
|
static uint8_t
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf)
|
||||||
|
{
|
||||||
|
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
|
||||||
|
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
|
||||||
|
|
||||||
|
return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -174,6 +191,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
|||||||
hal_tx_update_pcp_tid_generic,
|
hal_tx_update_pcp_tid_generic,
|
||||||
hal_tx_update_tidmap_prty_generic,
|
hal_tx_update_tidmap_prty_generic,
|
||||||
hal_rx_get_rx_fragment_number_9000,
|
hal_rx_get_rx_fragment_number_9000,
|
||||||
|
hal_rx_msdu_end_da_is_mcbc_get_9000,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
||||||
@@ -631,4 +649,3 @@ void hal_qcn9000_attach(struct hal_soc *hal_soc)
|
|||||||
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000;
|
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000;
|
||||||
hal_soc->ops = &qcn9000_hal_hw_txrx_ops;
|
hal_soc->ops = &qcn9000_hal_hw_txrx_ops;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
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