From ee90425ea7d9e973dd07f3f99cd96b9896602933 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 1 Nov 2019 12:37:55 +0530 Subject: [PATCH] disp: msm: dsi: add support to set continuous clock through phy For phy ver 4.0 chipsets, configure DSI controller and DSI PHY to force clk lane to HS mode always. This change was missed while propagating from 4.19 to 5.4. Change-Id: I60370034f7b9ed5d036d9d22f0807250afbcbcd5 Signed-off-by: Ritesh Kumar --- msm/dsi/dsi_display.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index 50d542b7ad..e5753aade5 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -1069,7 +1069,19 @@ static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display, display_for_each_ctrl(i, display) { ctrl = &display->ctrl[i]; - dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable); + + /* + * For phy ver 4.0 chipsets, configure DSI controller and + * DSI PHY to force clk lane to HS mode always whereas + * for other phy ver chipsets, configure DSI controller only. + */ + if (ctrl->phy->hw.ops.set_continuous_clk) { + dsi_ctrl_hs_req_sel(ctrl->ctrl, true); + dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable); + dsi_phy_set_continuous_clk(ctrl->phy, enable); + } else { + dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable); + } } }