disp: msm: increase delay times while waiting to turn off rscc clocks

RSC is timing out while checking for power control register,
increasing wait times only after a poms, removes this issue.

Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
此提交包含在:
Nilaan Gunabalachandran
2019-12-13 10:05:36 -05:00
提交者 Gerrit - the friendly Code Review server
父節點 1f331b536f
當前提交 eddae0d758
共有 3 個檔案被更改,包括 15 行新增1 行删除

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@@ -193,6 +193,7 @@ struct sde_rsc_bw_config {
* resource_refcount: Track rsc resource refcount
* profiling_supp: Indicates if HW has support for profiling counters
* profiling_en: Flag for rsc lpm profiling counters, true=enabled
* post_poms: bool if a panel mode change occurred
*/
struct sde_rsc_priv {
u32 version;
@@ -236,6 +237,8 @@ struct sde_rsc_priv {
atomic_t resource_refcount;
bool profiling_supp;
bool profiling_en;
bool post_poms;
};
/**