disp: msm: increase delay times while waiting to turn off rscc clocks

RSC is timing out while checking for power control register,
increasing wait times only after a poms, removes this issue.

Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This commit is contained in:
Nilaan Gunabalachandran
2019-12-13 10:05:36 -05:00
zatwierdzone przez Gerrit - the friendly Code Review server
rodzic 1f331b536f
commit eddae0d758
3 zmienionych plików z 15 dodań i 1 usunięć

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@@ -554,6 +554,8 @@ vsync_wait:
/* indicate wait for vsync for vid to cmd state switch & cfg update */
if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
rsc->current_state == SDE_RSC_CMD_STATE)) {
rsc->post_poms = true;
/* clear VSYNC timestamp for indication when update completes */
if (rsc->hw_ops.hw_vsync)
rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
@@ -707,6 +709,8 @@ vsync_wait:
/* indicate wait for vsync for vid to cmd state switch & cfg update */
if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
rsc->current_state == SDE_RSC_CMD_STATE)) {
rsc->post_poms = true;
/* clear VSYNC timestamp for indication when update completes */
if (rsc->hw_ops.hw_vsync)
rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
@@ -774,6 +778,7 @@ static int sde_rsc_switch_to_idle(struct sde_rsc_priv *rsc,
rc = CLK_MODE_SWITCH_SUCCESS;
} else if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_IDLE_STATE);
rsc->post_poms = false;
if (!rc) {
rpmh_mode_solver_set(rsc->rpmh_dev, true);
sde_rsc_set_data_bus_mode(&rsc->phandle,