disp: msm: increase delay times while waiting to turn off rscc clocks
RSC is timing out while checking for power control register, increasing wait times only after a poms, removes this issue. Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74 Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org> Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
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@@ -554,6 +554,8 @@ vsync_wait:
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/* indicate wait for vsync for vid to cmd state switch & cfg update */
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if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
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rsc->current_state == SDE_RSC_CMD_STATE)) {
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rsc->post_poms = true;
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/* clear VSYNC timestamp for indication when update completes */
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if (rsc->hw_ops.hw_vsync)
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rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
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@@ -707,6 +709,8 @@ vsync_wait:
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/* indicate wait for vsync for vid to cmd state switch & cfg update */
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if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||
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rsc->current_state == SDE_RSC_CMD_STATE)) {
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rsc->post_poms = true;
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/* clear VSYNC timestamp for indication when update completes */
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if (rsc->hw_ops.hw_vsync)
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rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
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@@ -774,6 +778,7 @@ static int sde_rsc_switch_to_idle(struct sde_rsc_priv *rsc,
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rc = CLK_MODE_SWITCH_SUCCESS;
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} else if (rsc->hw_ops.state_update) {
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rc = rsc->hw_ops.state_update(rsc, SDE_RSC_IDLE_STATE);
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rsc->post_poms = false;
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if (!rc) {
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rpmh_mode_solver_set(rsc->rpmh_dev, true);
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sde_rsc_set_data_bus_mode(&rsc->phandle,
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